From f91cca349464331fa5d34376725581cf2e8f0162 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 16 Aug 2026 20:14:46 -0700 Subject: [PATCH] Add regression tests for type identifiers as implicit nets Check that a type identifier is rejected rather than declared as an implicit net when used in a continuous assignment, primitive terminal, or ordered module port connection. Cover local typedefs, explicit imports, and activated wildcard imports. These contexts are currently rejected by the grammar. Keep the tests in place when type and hierarchy identifiers start using the same parser path. Signed-off-by: Lars-Peter Clausen --- ...tifier_implicit_assign_fail-iverilog-stderr.gold | 2 ++ ...entifier_implicit_gate_fail-iverilog-stderr.gold | 2 ++ ...entifier_implicit_port_fail-iverilog-stderr.gold | 2 ++ .../sv_type_identifier_implicit_assign_fail.v | 7 +++++++ .../sv_type_identifier_implicit_gate_fail.v | 11 +++++++++++ .../sv_type_identifier_implicit_port_fail.v | 13 +++++++++++++ ivtest/regress-vvp.list | 3 +++ .../sv_type_identifier_implicit_assign_fail.json | 6 ++++++ .../sv_type_identifier_implicit_gate_fail.json | 6 ++++++ .../sv_type_identifier_implicit_port_fail.json | 6 ++++++ 10 files changed, 58 insertions(+) create mode 100644 ivtest/gold/sv_type_identifier_implicit_assign_fail-iverilog-stderr.gold create mode 100644 ivtest/gold/sv_type_identifier_implicit_gate_fail-iverilog-stderr.gold create mode 100644 ivtest/gold/sv_type_identifier_implicit_port_fail-iverilog-stderr.gold create mode 100644 ivtest/ivltests/sv_type_identifier_implicit_assign_fail.v create mode 100644 ivtest/ivltests/sv_type_identifier_implicit_gate_fail.v create mode 100644 ivtest/ivltests/sv_type_identifier_implicit_port_fail.v create mode 100644 ivtest/vvp_tests/sv_type_identifier_implicit_assign_fail.json create mode 100644 ivtest/vvp_tests/sv_type_identifier_implicit_gate_fail.json create mode 100644 ivtest/vvp_tests/sv_type_identifier_implicit_port_fail.json diff --git a/ivtest/gold/sv_type_identifier_implicit_assign_fail-iverilog-stderr.gold b/ivtest/gold/sv_type_identifier_implicit_assign_fail-iverilog-stderr.gold new file mode 100644 index 000000000..8c7d95164 --- /dev/null +++ b/ivtest/gold/sv_type_identifier_implicit_assign_fail-iverilog-stderr.gold @@ -0,0 +1,2 @@ +ivltests/sv_type_identifier_implicit_assign_fail.v:6: syntax error +ivltests/sv_type_identifier_implicit_assign_fail.v:6: error: Syntax error in left side of continuous assignment. diff --git a/ivtest/gold/sv_type_identifier_implicit_gate_fail-iverilog-stderr.gold b/ivtest/gold/sv_type_identifier_implicit_gate_fail-iverilog-stderr.gold new file mode 100644 index 000000000..de76f2bc6 --- /dev/null +++ b/ivtest/gold/sv_type_identifier_implicit_gate_fail-iverilog-stderr.gold @@ -0,0 +1,2 @@ +ivltests/sv_type_identifier_implicit_gate_fail.v:10: syntax error +ivltests/sv_type_identifier_implicit_gate_fail.v:10: error: Invalid module item. diff --git a/ivtest/gold/sv_type_identifier_implicit_port_fail-iverilog-stderr.gold b/ivtest/gold/sv_type_identifier_implicit_port_fail-iverilog-stderr.gold new file mode 100644 index 000000000..52997b24b --- /dev/null +++ b/ivtest/gold/sv_type_identifier_implicit_port_fail-iverilog-stderr.gold @@ -0,0 +1,2 @@ +ivltests/sv_type_identifier_implicit_port_fail.v:12: syntax error +ivltests/sv_type_identifier_implicit_port_fail.v:12: error: Syntax error in instance port expression(s). diff --git a/ivtest/ivltests/sv_type_identifier_implicit_assign_fail.v b/ivtest/ivltests/sv_type_identifier_implicit_assign_fail.v new file mode 100644 index 000000000..b36b2e88b --- /dev/null +++ b/ivtest/ivltests/sv_type_identifier_implicit_assign_fail.v @@ -0,0 +1,7 @@ +// Check that a type identifier does not become an implicit net on the left +// side of a continuous assignment. + +module test; + typedef logic value; + assign value = 1'b1; +endmodule diff --git a/ivtest/ivltests/sv_type_identifier_implicit_gate_fail.v b/ivtest/ivltests/sv_type_identifier_implicit_gate_fail.v new file mode 100644 index 000000000..28b5f99fd --- /dev/null +++ b/ivtest/ivltests/sv_type_identifier_implicit_gate_fail.v @@ -0,0 +1,11 @@ +// Check that a type identifier does not become an implicit primitive terminal. + +package p; + typedef logic value; +endpackage + +module test; + import p::value; + wire result; + buf (result, value); +endmodule diff --git a/ivtest/ivltests/sv_type_identifier_implicit_port_fail.v b/ivtest/ivltests/sv_type_identifier_implicit_port_fail.v new file mode 100644 index 000000000..775494538 --- /dev/null +++ b/ivtest/ivltests/sv_type_identifier_implicit_port_fail.v @@ -0,0 +1,13 @@ +// Check that a type identifier does not become an implicit module connection. + +package p; + typedef logic value; +endpackage + +module M(input wire data); +endmodule + +module test; + import p::*; + M i_m(value); +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index ed424ff34..03bf20426 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -523,6 +523,9 @@ sv_type_identifier_function_name vvp_tests/sv_type_identifier_function_name.json sv_type_identifier_generate_label_name vvp_tests/sv_type_identifier_generate_label_name.json sv_type_identifier_genvar_name vvp_tests/sv_type_identifier_genvar_name.json sv_type_identifier_hier_fail vvp_tests/sv_type_identifier_hier_fail.json +sv_type_identifier_implicit_assign_fail vvp_tests/sv_type_identifier_implicit_assign_fail.json +sv_type_identifier_implicit_gate_fail vvp_tests/sv_type_identifier_implicit_gate_fail.json +sv_type_identifier_implicit_port_fail vvp_tests/sv_type_identifier_implicit_port_fail.json sv_type_identifier_inherited_property_shadow vvp_tests/sv_type_identifier_inherited_property_shadow.json sv_type_identifier_modport_name vvp_tests/sv_type_identifier_modport_name.json sv_type_identifier_modport_named_port vvp_tests/sv_type_identifier_modport_named_port.json diff --git a/ivtest/vvp_tests/sv_type_identifier_implicit_assign_fail.json b/ivtest/vvp_tests/sv_type_identifier_implicit_assign_fail.json new file mode 100644 index 000000000..1dde06962 --- /dev/null +++ b/ivtest/vvp_tests/sv_type_identifier_implicit_assign_fail.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_type_identifier_implicit_assign_fail.v", + "gold" : "sv_type_identifier_implicit_assign_fail", + "iverilog-args" : [ "-g2005-sv" ] +} diff --git a/ivtest/vvp_tests/sv_type_identifier_implicit_gate_fail.json b/ivtest/vvp_tests/sv_type_identifier_implicit_gate_fail.json new file mode 100644 index 000000000..e2ce94855 --- /dev/null +++ b/ivtest/vvp_tests/sv_type_identifier_implicit_gate_fail.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_type_identifier_implicit_gate_fail.v", + "gold" : "sv_type_identifier_implicit_gate_fail", + "iverilog-args" : [ "-g2005-sv" ] +} diff --git a/ivtest/vvp_tests/sv_type_identifier_implicit_port_fail.json b/ivtest/vvp_tests/sv_type_identifier_implicit_port_fail.json new file mode 100644 index 000000000..d59c0de3c --- /dev/null +++ b/ivtest/vvp_tests/sv_type_identifier_implicit_port_fail.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_type_identifier_implicit_port_fail.v", + "gold" : "sv_type_identifier_implicit_port_fail", + "iverilog-args" : [ "-g2005-sv" ] +}