Initial process have wait at the end

(do it properly this time rather than a hack :-)

tgt-vhdl/process.cc

@@ -33,7 +33,13 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
 {
    vhdl_process *vhdl_proc = new vhdl_process();
 
-   // TODO: Add statements
+   // Initial processes are translated to VHDL processes with
+   // no sensitivity list and and indefinite wait statement at
+   // the end
+   if (ivl_process_type(proc) == IVL_PR_INITIAL) {
+      vhdl_wait_stmt *wait = new vhdl_wait_stmt();
+      vhdl_proc->add_stmt(wait);
+   }
    
    // Add a comment indicating where it came from
    ivl_scope_t scope = ivl_process_scope(proc);

tgt-vhdl/vhdl_element.cc

@@ -206,10 +206,7 @@ void vhdl_process::emit(std::ofstream &of, int level) const
    newline(of, level);
    // ...declarations...
    of << "begin";
-   newline(of, level);
-   // ...statements...
-   of << "  wait;";   // Just to stop the simulation hanging
-   newline(of, level);
+   emit_children<vhdl_seq_stmt>(of, stmts_, level);
    of << "end process;";
    newline(of, level);
 }
@@ -261,3 +258,12 @@ void vhdl_component_decl::emit(std::ofstream &of, int level) const
    newline(of, level);
    of << "end component;";
 }
+
+
+//////// WAIT STATEMENT ////////
+
+void vhdl_wait_stmt::emit(std::ofstream &of, int level) const
+{
+   // TODO: There are lots of different types of `wait'
+   of << "wait;";
+}

tgt-vhdl/vhdl_element.hh

@@ -68,6 +68,17 @@ public:
 
 typedef std::list<vhdl_seq_stmt*> seq_stmt_list_t;
 
+
+/*
+ * Delay simulation indefinitely, until an event, or for a
+ * specified time.
+ */
+class vhdl_wait_stmt : public vhdl_seq_stmt {
+public:
+   void emit(std::ofstream &of, int level) const;
+};
+
+
 /*
  * A declaration of some sort (variable, component, etc.).
  * Declarations have names, which is the identifier of the variable,