85 lines
2.8 KiB
C++
85 lines
2.8 KiB
C++
/*
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* VHDL code generation for processes.
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*
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* Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "vhdl_target.h"
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#include "vhdl_element.hh"
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#include <iostream>
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#include <cassert>
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#include <sstream>
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/*
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* Convert a Verilog process to VHDL and add it to the architecture
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* of the given entity.
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*/
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static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
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{
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vhdl_process *vhdl_proc = new vhdl_process();
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// Initial processes are translated to VHDL processes with
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// no sensitivity list and and indefinite wait statement at
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// the end
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if (ivl_process_type(proc) == IVL_PR_INITIAL) {
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vhdl_wait_stmt *wait = new vhdl_wait_stmt();
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vhdl_proc->add_stmt(wait);
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}
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// Add a comment indicating where it came from
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ivl_scope_t scope = ivl_process_scope(proc);
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const char *type = ivl_process_type(proc) == IVL_PR_INITIAL
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? "initial" : "always";
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std::ostringstream ss;
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ss << "Generated from " << type << " process in ";
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ss << ivl_scope_tname(scope);
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vhdl_proc->set_comment(ss.str());
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// Store it in the entity's architecture
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ent->get_arch()->add_stmt(vhdl_proc);
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return 0;
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}
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int draw_process(ivl_process_t proc, void *cd)
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{
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ivl_scope_t scope = ivl_process_scope(proc);
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const char *scope_name = ivl_scope_name(scope);
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// A process should occur in a module scope, therefore it
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// should have already been assigned a VHDL entity
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assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
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vhdl_entity *ent = find_entity(ivl_scope_tname(scope));
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assert(ent != NULL);
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// If the scope this process belongs to is the same as the
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// VHDL entity was generated from, then create a VHDL process
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// from this Verilog process. This ensures that each process
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// is translated at most once, no matter how many times it
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// appears in the hierarchy.
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if (ent->get_derived_from() == scope_name) {
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std::cout << "New process encountered in " << scope_name << std::endl;
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return generate_vhdl_process(ent, proc);
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}
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else {
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std::cout << "Ignoring already seen process in ";
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std::cout << scope_name << std::endl;
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return 0;
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}
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}
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