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Lars-Peter Clausen
9bbdb0da0e
Check that automatic variables referenced through an assignment pattern in a procedural `force` statement are rejected. Signed-off-by: Lars-Peter Clausen <[email protected]>
20 lines
324 B
Verilog
20 lines
324 B
Verilog
// Check that assignment patterns cannot reference automatic variables in
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// procedural force statements.
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module test;
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reg [3:0] result;
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task automatic t;
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input [3:0] value;
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begin
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force result = '{value[3], value[2], value[1], value[0]};
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end
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endtask
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initial begin
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t(4'ha);
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end
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endmodule
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