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vhdlpp: generics without a default value are set to 1'bx.

This commit is contained in:
Larry Doolittle 2015-05-16 00:40:26 +02:00 committed by Maciej Suminski
parent 25458b8cc2
commit 9231ad51a4
1 changed files with 6 additions and 3 deletions
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7
vhdlpp/entity_emit.cc
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@ -50,10 +50,13 @@ int Entity::emit(ostream&out)
const InterfacePort*curp = *cur; const InterfacePort*curp = *cur;
if (cur != parms_.begin()) if (cur != parms_.begin())
out << ", "; out << ", ";
out << "parameter \\" << curp->name << " "; out << "parameter \\" << curp->name << " = ";
if(curp->expr) { if(curp->expr) {
out << "= ";
errors += curp->expr->emit(out, this, 0); errors += curp->expr->emit(out, this, 0);
} else {
// Unlike VHDL, Verilog module parameter port list
// elements are always assignments. Fill in the blank.
out << "1'bx";
} }
} }
out << ") "; out << ") ";