From 9231ad51a41f3f81f2b4189c350410aec7ffe97a Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Sat, 16 May 2015 00:40:26 +0200 Subject: [PATCH] vhdlpp: generics without a default value are set to 1'bx. --- vhdlpp/entity_emit.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/vhdlpp/entity_emit.cc b/vhdlpp/entity_emit.cc index fd2077fdc..62acac193 100644 --- a/vhdlpp/entity_emit.cc +++ b/vhdlpp/entity_emit.cc @@ -50,11 +50,14 @@ int Entity::emit(ostream&out) const InterfacePort*curp = *cur; if (cur != parms_.begin()) out << ", "; - out << "parameter \\" << curp->name << " "; + out << "parameter \\" << curp->name << " = "; if(curp->expr) { - out << "= "; errors += curp->expr->emit(out, this, 0); - } + } else { + // Unlike VHDL, Verilog module parameter port list + // elements are always assignments. Fill in the blank. + out << "1'bx"; + } } out << ") "; }