From 37ef14b1c87697ea32cda31743c960c3ffebdb52 Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Sat, 29 Oct 2011 14:47:39 -0700
Subject: [PATCH] Implement VHDL conf_std_logic_vector() as SystemVerilog size
 cast.

---
 vhdlpp/expression_emit.cc | 8 ++++++++
 vhdlpp/library.cc         | 9 +++++++++
 2 files changed, 17 insertions(+)

diff --git a/vhdlpp/expression_emit.cc b/vhdlpp/expression_emit.cc
index 1777da7fa..ed81e3b07 100644
--- a/vhdlpp/expression_emit.cc
+++ b/vhdlpp/expression_emit.cc
@@ -396,6 +396,14 @@ int ExpFunc::emit(ostream&out, Entity*ent, Architecture*arc)
 	    errors += argv_[0]->emit(out, ent, arc);
 	    out << "))";
 
+      } else if (name_ == "conv_std_logic_vector" && argv_.size() == 2) {
+	    int64_t use_size;
+	    bool rc = argv_[1]->evaluate(ent, arc, use_size);
+	    ivl_assert(*this, rc);
+	    out << use_size << "'(";
+	    errors += argv_[0]->emit(out, ent, arc);
+	    out << ")";
+
       } else {
 	    out << "\\" << name_ << " (";
 	    for (size_t idx = 0; idx < argv_.size() ; idx += 1) {
diff --git a/vhdlpp/library.cc b/vhdlpp/library.cc
index 08b312fa8..776789eb1 100644
--- a/vhdlpp/library.cc
+++ b/vhdlpp/library.cc
@@ -259,6 +259,10 @@ static void import_ieee_use_std_logic_1164(ActiveScope*res, perm_string name)
       }
 }
 
+static void import_ieee_use_std_logic_arith(ActiveScope*, perm_string)
+{
+}
+
 static void import_ieee_use_numeric_bit(ActiveScope*res, perm_string name)
 {
       bool all_flag = name=="all";
@@ -298,6 +302,11 @@ static void import_ieee_use(ActiveScope*res, perm_string package, perm_string na
 	    return;
       }
 
+      if (package == "std_logic_arith") {
+	    import_ieee_use_std_logic_arith(res, name);
+	    return;
+      }
+
       if (package == "numeric_bit") {
 	    import_ieee_use_numeric_bit(res, name);
 	    return;