diff --git a/ivtest/ivltests/module_nonansi_fail1.v b/ivtest/ivltests/module_nonansi_fail1.v
new file mode 100644
index 000000000..5f1cde8e1
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail1.v
@@ -0,0 +1,7 @@
+// Check that declaring multiple non-ANSI module ports with the same name is an
+// error. Even if they both have an implicit type.
+
+module test(x);
+  input x;
+  input x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail10.v b/ivtest/ivltests/module_nonansi_fail10.v
new file mode 100644
index 000000000..3b714d28b
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail10.v
@@ -0,0 +1,7 @@
+// Check that declaring a non-ANSI module port with an explicit type for a
+// signal that was previously declared as a real variable is an error.
+
+module test(x);
+  real x;
+  output integer x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail11.v b/ivtest/ivltests/module_nonansi_fail11.v
new file mode 100644
index 000000000..77d3c44f1
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail11.v
@@ -0,0 +1,9 @@
+// Check that declaring multiple non-ANSI module ports with an implicit type and
+// the same name is an error. Even if the signal was previously declared as a
+// net.
+
+module test(x);
+  wire x;
+  input x;
+  input x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail12.v b/ivtest/ivltests/module_nonansi_fail12.v
new file mode 100644
index 000000000..ad5b2dafb
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail12.v
@@ -0,0 +1,10 @@
+// Check that declaring multiple non-ANSI module ports with an implicit type and
+// the same name is an error. Even if the signal was previously declared as a
+// integer typed net.
+
+module test(x);
+  wire integer x;
+  input x;
+  input x;
+
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail13.v b/ivtest/ivltests/module_nonansi_fail13.v
new file mode 100644
index 000000000..4d2cd2733
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail13.v
@@ -0,0 +1,8 @@
+// Check that declaring multiple non-ANSI module output ports with an explicit
+// type is an error. Even if the types are the same.
+
+module test(x);
+  output integer x;
+  output integer x;
+
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail2.v b/ivtest/ivltests/module_nonansi_fail2.v
new file mode 100644
index 000000000..2e84e422b
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail2.v
@@ -0,0 +1,8 @@
+// Check that declaring a net multiple times for a signal that was previously
+// declared as a non-ANSI module port is an error.
+
+module test(x);
+  input x;
+  wire x;
+  wire x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail3.v b/ivtest/ivltests/module_nonansi_fail3.v
new file mode 100644
index 000000000..21c078034
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail3.v
@@ -0,0 +1,8 @@
+// Check that declaring a variable multiple times for a signal that was
+// previously declared as a non-ANSI module port is an error.
+
+module test(x);
+  output x;
+  reg x;
+  reg x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail4.v b/ivtest/ivltests/module_nonansi_fail4.v
new file mode 100644
index 000000000..3303683f2
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail4.v
@@ -0,0 +1,8 @@
+// Check that declaring both a net and a variable for a signal that was
+// previously declared as a non-ANSI module port is an error.
+
+module test(x);
+  input x;
+  wire x;
+  reg x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail5.v b/ivtest/ivltests/module_nonansi_fail5.v
new file mode 100644
index 000000000..97c664cc0
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail5.v
@@ -0,0 +1,8 @@
+// Check that declaring an integer typed non-ANSI module port for signal that
+// was previously declared as a net is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  wire integer x;
+  input integer x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail6.v b/ivtest/ivltests/module_nonansi_fail6.v
new file mode 100644
index 000000000..9ce2c6fca
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail6.v
@@ -0,0 +1,8 @@
+// Check that declaring an integer typed net for a signal that was previously
+// declared as a non-ANSI module port is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  input integer x;
+  wire integer x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail7.v b/ivtest/ivltests/module_nonansi_fail7.v
new file mode 100644
index 000000000..21f50a184
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail7.v
@@ -0,0 +1,8 @@
+// Check that declaring a real typed variable for a signal that was previously
+// declared as a non-ANSI module port is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  output real x;
+  real x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail8.v b/ivtest/ivltests/module_nonansi_fail8.v
new file mode 100644
index 000000000..7603854d0
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail8.v
@@ -0,0 +1,8 @@
+// Check that declaring a real typed non-ANSI module port for a signal that was
+// previously declared as a variable is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  real x;
+  output real x;
+endmodule
diff --git a/ivtest/ivltests/module_nonansi_fail9.v b/ivtest/ivltests/module_nonansi_fail9.v
new file mode 100644
index 000000000..6240fca3d
--- /dev/null
+++ b/ivtest/ivltests/module_nonansi_fail9.v
@@ -0,0 +1,7 @@
+// Check that declaring an integer typed variable for a signal that was previously
+// declared as a real typed non-ANSI module port is an error.
+
+module test(x);
+  output real x;
+  integer x;
+endmodule
diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list
index bf0982966..15c51ccb0 100644
--- a/ivtest/regress-vlg.list
+++ b/ivtest/regress-vlg.list
@@ -654,6 +654,19 @@ module_inout_port_list_def CE			ivltests # inout ports do not support default va
 module_inout_port_type	CE			ivltests
 module_input_port_list_def CE			ivltests # input ports only support default values in SV
 module_input_port_type	CE			ivltests
+module_nonansi_fail1	CE			ivltests
+module_nonansi_fail2	CE			ivltests
+module_nonansi_fail3	CE			ivltests
+module_nonansi_fail4	CE			ivltests
+module_nonansi_fail5	CE			ivltests
+module_nonansi_fail6	CE			ivltests
+module_nonansi_fail7	CE			ivltests
+module_nonansi_fail8	CE			ivltests
+module_nonansi_fail9	CE			ivltests
+module_nonansi_fail10	CE			ivltests
+module_nonansi_fail11	CE			ivltests
+module_nonansi_fail12	CE			ivltests
+module_nonansi_fail13	CE			ivltests
 module_nonansi_integer1	normal			ivltests
 module_nonansi_integer2	normal			ivltests
 module_nonansi_integer_fail CE			ivltests