2001-08-28 06:14:20 +02:00
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/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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2001-08-31 04:59:06 +02:00
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#ident "$Id: d-generic.c,v 1.2 2001/08/31 02:59:06 steve Exp $"
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2001-08-28 06:14:20 +02:00
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# include "device.h"
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# include "fpga_priv.h"
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# include <assert.h>
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/*
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* This is the device emitter for the most generic FPGA. It doesn't
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* know anything special about device types, so can't handle complex
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* logic.
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*/
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static void generic_show_logic(ivl_net_logic_t net)
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{
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char name[1024];
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ivl_nexus_t nex;
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mangle_logic_name(net, name, sizeof name);
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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assert(ivl_logic_pins(net) == 3);
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fprintf(xnf, "SYM, %s, AND, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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draw_pin(nex, "O", 'O');
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nex = ivl_logic_pin(net, 1);
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draw_pin(nex, "I0", 'I');
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nex = ivl_logic_pin(net, 2);
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draw_pin(nex, "I1", 'I');
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2001-08-31 04:59:06 +02:00
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fprintf(xnf, "END\n");
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2001-08-28 06:14:20 +02:00
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break;
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case IVL_LO_BUF:
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assert(ivl_logic_pins(net) == 2);
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fprintf(xnf, "SYM, %s, BUF, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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draw_pin(nex, "O", 'O');
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nex = ivl_logic_pin(net, 1);
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draw_pin(nex, "I", 'I');
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2001-08-31 04:59:06 +02:00
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fprintf(xnf, "END\n");
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2001-08-28 06:14:20 +02:00
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break;
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default:
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fprintf(stderr, "fpga.tgt: unknown logic type %u\n",
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ivl_logic_type(net));
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break;
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}
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}
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static void generic_show_dff(ivl_lpm_t net)
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{
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char name[1024];
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ivl_nexus_t nex;
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mangle_lpm_name(net, name, sizeof name);
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fprintf(xnf, "SYM, %s, DFF, LIBVER=2.0.0\n", name);
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nex = ivl_lpm_q(net, 0);
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draw_pin(nex, "Q", 'O');
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nex = ivl_lpm_data(net, 0);
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draw_pin(nex, "D", 'I');
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nex = ivl_lpm_clk(net);
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draw_pin(nex, "CLK", 'I');
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fprintf(xnf, "END\n");
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}
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const struct device_s d_generic = {
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generic_show_logic,
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generic_show_dff
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};
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/*
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* $Log: d-generic.c,v $
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2001-08-31 04:59:06 +02:00
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* Revision 1.2 2001/08/31 02:59:06 steve
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* Add root port SIG records.
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*
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2001-08-28 06:14:20 +02:00
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* Revision 1.1 2001/08/28 04:14:20 steve
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* Add the fpga target.
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*
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*/
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