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Updated iCE40 PLL documentation (markdown)

Sylvain "tnt" Munaut 2024-03-30 17:55:36 +01:00
parent 7dd9a4837c
commit f453647c35
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iCE40-PLL-documentation.md

@ -29,7 +29,7 @@ Sequence would be :
* Wait for `PLL_LOCK`
* Release the reset of your logic clocked by PLL output
The configuration word is 25 bits, or 26 bits for the UP5k :
The configuration word is 26 bits, or 27 bits for the UP5k :
```
[ 26] ShiftReg[1] (UP5k only)