diff --git a/iCE40-PLL-documentation.md b/iCE40-PLL-documentation.md
index 95f663e..6919f6d 100644
--- a/iCE40-PLL-documentation.md
+++ b/iCE40-PLL-documentation.md
@@ -29,7 +29,7 @@ Sequence would be :
 * Wait for `PLL_LOCK`
 * Release the reset of your logic clocked by PLL output
 
-The configuration word is 25 bits, or 26 bits for the UP5k :
+The configuration word is 26 bits, or 27 bits for the UP5k :
 
 ```
 [   26] ShiftReg[1]  (UP5k only)