From f453647c3551d954251dc03e2e3ffc9ef52269f8 Mon Sep 17 00:00:00 2001 From: "Sylvain \"tnt\" Munaut" Date: Sat, 30 Mar 2024 17:55:36 +0100 Subject: [PATCH] Updated iCE40 PLL documentation (markdown) --- iCE40-PLL-documentation.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/iCE40-PLL-documentation.md b/iCE40-PLL-documentation.md index 95f663e..6919f6d 100644 --- a/iCE40-PLL-documentation.md +++ b/iCE40-PLL-documentation.md @@ -29,7 +29,7 @@ Sequence would be : * Wait for `PLL_LOCK` * Release the reset of your logic clocked by PLL output -The configuration word is 25 bits, or 26 bits for the UP5k : +The configuration word is 26 bits, or 27 bits for the UP5k : ``` [ 26] ShiftReg[1] (UP5k only)