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851 Commits

Author SHA1 Message Date
gatecat b5f9560233 icetime: Ignore false paths through LUTs based on function 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-29 13:24:51 +01:00
gatecat 1d8e1a8f58
Merge pull request #293 from YosysHQ/gatecat/cb121-fix 
icebox: cb121 does have a PLL
 2022-03-25 16:31:02 +00:00
gatecat e23274a9dd icebox: cb121 does have a PLL 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-25 15:52:44 +00:00
Maik Merten c9ad6ca881 icetime: indent with tabs 2022-03-05 17:36:21 +01:00
Maik Merten 5b5c7ce599 icetime PCF parsing: handle -pullup and -pullup_resistor in set_io constraints 2022-03-05 17:33:14 +01:00
gatecat 8fa85d5ee3
Merge pull request #289 from osresearch/bitstream-pr 
docs/format.html: document bram/cram read-back commands
 2022-01-22 19:11:57 +00:00
Trammell Hudson 5b5d7bb3ce docs/format.html: document bram/cram read-back commands 
The Lattice tools use these additional commands to read-back the BRAM
and CRAM after programming to validate that it was written correctly.
`iceprog` doesn't use this right now, so this is just for documentation
purposes.

Signed-off-by: Trammell Hudson <hudson@trmm.net>
 2022-01-22 18:46:24 +01:00
Catherine 3b7b199131
Merge pull request #287 from projf/update-url 
Update URL for web site.
 2022-01-02 02:31:16 +00:00
Sylvain Munaut 98d8bee04f iceprog: Use open-drain output to drive SS and Reset line 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-12-17 19:45:34 +01:00
Sylvain Munaut c5a8beffec iceprog: Improve reset to disable both CRM and QPI 
It's hard to cover 100% of cases, but this seems to improve
probability that a reset works, at least for me on the icebreaker.

Some other flash have a different QPI disable command though :/

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-12-17 19:45:34 +01:00
Sylvain Munaut 502d847b41 iceprog: Add option that set QE=1 bit in SR2 
This is useful when testing litex SoC that rely on that bit being set

The setting is non-volatile so it only needs to be done once in case
you happen to have used a flash chip that's not by default QE=1

(This has been designed for winbond flash. Others might use
 different bit ...)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-12-17 19:44:24 +01:00
Will Green b5dbe11335
Update URL for web site. 2021-11-28 19:26:21 +00:00
Miodrag Milanović 83b8ef947f
Merge pull request #282 from jkiv/iceprog-ignorig-fix 
[iceprog] Fixed typo in error message: "Ignorig"
 2021-09-06 11:14:46 +02:00
Miodrag Milanovic 9880f6e2dd Update variable name to PYTHON3 2021-09-06 11:11:52 +02:00
Miodrag Milanović f14a7fb4ca
Merge pull request #239 from xobs/python-bin-name 
Use $(PYTHON) in Makefiles instead of `python3`
 2021-09-06 11:08:23 +02:00
Miodrag Milanovic 9fe28369aa Fixes for macOS 2021-09-06 11:07:42 +02:00
Claire Xen b93cb16bb0
Merge pull request #276 from esden/progress 
iceprog: Add write and read progress indication.
 2021-08-30 16:01:56 +02:00
Jon Kivinen 97b6e276e8
[iceprog] Fixed typo in error message: "Ignorig" 2021-05-03 19:31:39 -04:00
gatecat c495861c19 Use --recursive for nextpnr clone 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-09 09:51:12 +00:00
whitequark 0dfc7130bb
Merge pull request #279 from YosysHQ/update-gitignore 
Add more build products to .gitignore
 2021-03-05 04:46:24 -08:00
whitequark 529759c4bd Add more build products to .gitignore. 2021-03-05 12:43:57 +00:00
David Williams e368f15a7f Add an option (-p) to force use of SB_PLL40_PAD 
When a clock is applied to a dedicated clock pin, SB_PLL40_CORE is no longer the correct primitive to use.

Also the name of the clock input must be PACKAGEPIN (rather than REFERENCECLK)
 2021-02-05 07:35:50 -08:00
Piotr Esden-Tempski 549fd314a0 iceprog: Add write and read progress indication. 2021-01-16 22:58:29 -08:00
David Shah 7afc64b480
Merge pull request #275 from nils1603/feature/ip_support_u4k 
added I2C and SPI for u4k to database
 2020-12-04 21:39:13 +00:00
Nils Albartus d969c333d0 added I2C and SPI for u4k to database 2020-12-04 16:47:05 +01:00
Claire Wolf da52117ccd Fix links and email addr in index.html 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-19 10:35:39 +02:00
Claire Wolf f8c82074d2 Use YosysHQ in index.html 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-19 10:32:27 +02:00
Claire Wolf 62041701ce Use Claire in index.html 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-19 10:30:46 +02:00
Miodrag Milanović d123087756
Merge pull request #264 from YosysHQ/mmicko/improvements 
Support rest of parts by icetime
 2020-07-08 20:38:52 +02:00
Miodrag Milanovic af42a45b91 Enable rest of lattice parts in icetime 2020-07-08 19:48:11 +02:00
Miodrag Milanovic 4b54d341de Prevent rebuilding timing files 2020-07-08 19:28:18 +02:00
David Shah 59ace92436
Merge pull request #263 from YosysHQ/fix_vlog_up5k 
Fix icebox_vlog for up5k
 2020-07-02 13:32:02 +01:00
David Shah 4bc68c9620 Fix icebox_vlog for up5k 
Since ce1d811, SHIFTREG_DIV_MODE is now 2 bits for the up5k

Signed-off-by: David Shah <dave@ds0.me>
 2020-06-29 19:51:06 +01:00
clairexen ed978e24e2
Merge pull request #262 from whitequark/icebram-fix 
Fix icebram
 2020-06-26 16:01:51 +02:00
whitequark 7ed94f5170 icebram: add WASI platform support. 2020-06-26 11:30:00 +00:00
whitequark f8b8ea0f3c icebram: refactor seeding logic. 2020-06-26 11:30:00 +00:00
whitequark 3205180fd9 Revert "Make icebram deterministic" 
This reverts commit 2679c91b8a.
 2020-06-26 10:38:41 +00:00
Claire Wolf f138ade065
Merge pull request #257 from smunaut/ice40_shiftreg_div_mode 
icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE
 2020-06-25 18:35:48 +02:00
Claire Wolf 9e44d9f1d2
Merge pull request #261 from whitequark/icepack-usage 
icepack: show program name in usage
 2020-06-25 18:31:40 +02:00
Claire Wolf c4e9b19b0c
Merge pull request #260 from whitequark/patch-1 
Make icebram deterministic
 2020-06-25 18:31:18 +02:00
Claire Wolf cc24caa4c6
Merge pull request #254 from per-gron/fix-oob 
Fix array out of bounds access bug
 2020-06-25 18:26:00 +02:00
Claire Wolf 3ce2673009
Merge pull request #253 from SolraBizna/dummy-header-targets 
Use -MP to eliminate one way that -MD can fatally confuse make
 2020-06-25 18:24:48 +02:00
Claire Wolf ef4489835c
Merge pull request #256 from emaste/master 
icetime: avoid string + int Clang warning
 2020-06-25 18:24:09 +02:00
whitequark a4b1194b3a icepack: show program name in usage. 2020-06-24 19:57:22 +00:00
whitequark 2679c91b8a
Make icebram deterministic 2020-06-23 07:42:15 +00:00
Sylvain Munaut ce1d811d21 icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k 
This allows selection of the div-by-5 mode of the PLL.
This bit can't be fuzzed because it's not supported by the lattice
tools at all ...

This only works for sure on the UP5k.

I tested HX8k and it didn't support it, so I'm only adding this on
the known working FPGA.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-03 10:45:31 +02:00
Ed Maste e52149944e icetime: avoid string + int Clang warning 
Clang warns that "adding 'int' to a string does not append to the string".
Although a false positive it's trivially avoided by using the array index
equivalent &PREFIX[1].
 2020-05-28 13:33:47 -04:00
Per Grön 4590de5c7f Fix array out of bounds access bug 
This is triggered for example when icetime is invoked with an empty design.
 2020-05-25 16:57:01 +02:00
Solra Bizna 41f75569e3
Add -MP to CFLAGS and CXXFLAGS, making it harder for make to get confused out of even trying to build 2020-05-09 02:40:08 -06:00
Claire Wolf cd2610e0fa Fix compiler warning in icepll 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-22 18:39:38 +02:00