15 Commits

Author	SHA1	Message	Date
David Shah	a59472812c	Remove seperate 5k RAM DB and share with 8k instead ... This should ensure that the 5k RAM routing entries are now complete, fixing #115	2018-01-16 15:17:20 +00:00
David Shah	96b527bfef	Create icefuzz scripts for DSP and 5k	2017-11-17 15:07:52 +00:00
David Shah	629621642f	Preparations for DSP and IpCon fuzzing	2017-11-08 16:05:42 +00:00
David Shah	e9e9d0e9cb	Share glb_netwk data between 5k and 8k parts	2017-10-29 16:14:15 +00:00
David Shah	2a7c32e49a	Add ColBufCtrl bits to database for 5k parts	2017-10-25 10:50:36 +01:00
Clifford Wolf	72d2a02810	Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from database	2017-07-31 15:55:07 +02:00
Scott Shawcroft	a25c8679ac	More work figuring out values in icebox.py	2017-06-23 22:53:54 -07:00
Scott Shawcroft	58a6110be1	Add icefuzz support for the UP5K and rework underlying device specification for more flexibility.	2017-06-22 17:38:38 -07:00
Clifford Wolf	314628ffd3	Disable propagation of LP384 ieren bits into iceboxdb.py	2017-03-11 11:16:23 +01:00
Clifford Wolf	2fe704227f	Fuzzed RamCascade bits	2016-01-09 12:45:43 +01:00
Clifford Wolf	9c9983cff8	Added lutff_i/lout net to model	2015-12-04 11:46:08 +01:00
Clifford Wolf	a110369832	Added 1k timings	2015-09-27 10:54:19 +02:00
Clifford Wolf	f6f96a26e0	icefuzz: python 3	2015-08-22 09:42:57 +02:00
Clifford Wolf	4c1335f51e	Replaced calls to "python" with "python2"	2015-07-30 10:15:48 +02:00
Clifford Wolf	48154cb6f4	Imported full dev sources	2015-07-18 13:10:40 +02:00