luke
/
icestorm
mirror of https://github.com/YosysHQ/icestorm.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fuzzed RamCascade bits

This commit is contained in:
Clifford Wolf 2016-01-09 12:45:43 +01:00
parent c4e5a5e57f
commit 2fe704227f
7 changed files with 128 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
icebox/icebox_html.py
View File

@ -254,6 +254,8 @@ configuration bits it has and how it is connected to its neighbourhood.</p>""" %
bitmap_cells[idx1][idx2]["label"] = "A"
elif entry[1].startswith("RamConfig"):
bitmap_cells[idx1][idx2]["label"] = "M"
elif entry[1].startswith("RamCascade"):
bitmap_cells[idx1][idx2]["label"] = "M"
elif entry[1].startswith("PLL"):
bitmap_cells[idx1][idx2]["label"] = "P"
else:

8
icebox/iceboxdb.py
View File

@ -3896,6 +3896,10 @@ B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
"""
database_ramt_txt = """
B0[0] NegClk
B5[7] RamCascade CBIT_4
B4[7] RamCascade CBIT_5
B7[7] RamCascade CBIT_6
B6[7] RamCascade CBIT_7
B1[7] RamConfig CBIT_0
B0[7] RamConfig CBIT_1
B3[7] RamConfig CBIT_2
@ -6759,6 +6763,10 @@ B12[7] ColBufCtrl 8k_glb_netwk_5
B15[7] ColBufCtrl 8k_glb_netwk_6
B14[7] ColBufCtrl 8k_glb_netwk_7
B0[0] NegClk
B5[7] RamCascade CBIT_4
B4[7] RamCascade CBIT_5
B7[7] RamCascade CBIT_6
B6[7] RamCascade CBIT_7
B1[7] RamConfig CBIT_0
B0[7] RamConfig CBIT_1
B3[7] RamConfig CBIT_2

1
icefuzz/Makefile
View File

@ -15,6 +15,7 @@ TESTS += gbio2
TESTS += prim
TESTS += fflogic
TESTS += ram40
TESTS += mem
TESTS += pll
EIGTHK = _8k

36
icefuzz/cached_ramt.txt
View File

@ -3459,6 +3459,42 @@
(7 1) Ram config bit: MEMT_bram_cbit_0
(7 2) Ram config bit: MEMT_bram_cbit_3
(7 3) Ram config bit: MEMT_bram_cbit_2
(7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux02_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5
(7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC01_inmux02_bram_cbit_4
(7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4
(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux02_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux02_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7
(7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC00_inmux02_bram_cbit_6
(7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC01_inmux02_bram_cbit_6
(7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6
(8 0) routing sp4_h_l_36 <X> sp4_h_r_1
(8 0) routing sp4_h_l_40 <X> sp4_h_r_1
(8 0) routing sp4_v_b_1 <X> sp4_h_r_1

36
icefuzz/cached_ramt_8k.txt
View File

@ -3465,6 +3465,42 @@
(7 15) Column buffer control bit: MEMT_colbuf_cntl_6
(7 2) Ram config bit: MEMT_bram_cbit_3
(7 3) Ram config bit: MEMT_bram_cbit_2
(7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5
(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5
(7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4
(7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4
(7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4
(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7
(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_7
(7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC06_inmux02_bram_cbit_6
(7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6
(7 7) Cascade bit: MEMT_LC07_inmux02_bram_cbit_6
(7 8) Column buffer control bit: MEMT_colbuf_cntl_1
(7 9) Column buffer control bit: MEMT_colbuf_cntl_0
(8 0) routing sp4_h_l_36 <X> sp4_h_r_1

6
icefuzz/database.py
View File

@ -53,7 +53,11 @@ def read_database(filename, tile_type):
if match:
raw_db.append((bit, ("buffer", "wire_logic_cluster/lc_%d/lout" % (int(match.group(1))-1), "input_2_%s" % match.group(1))))
else:
raw_db.append((bit, (line[0], line[1])))
match = re.match("MEMT_LC\d+_inmux\d+_bram_cbit_(\d+)", line[1])
if match:
raw_db.append((bit, ("RamCascade", "CBIT_%d" % int(match.group(1)))))
else:
raw_db.append((bit, (line[0], line[1])))
elif line[0] == "RamConfig":
if line[1] == "MEMB_Power_Up_Control": line[1] = "PowerUp"
line[1] = re.sub(r"MEMT_bram_cbit_", "CBIT_", line[1])

40
icefuzz/make_mem.py Normal file
View File

@ -0,0 +1,40 @@
#!/usr/bin/env python3
from fuzzconfig import *
import numpy as np
import os
os.system("rm -rf work_mem")
os.mkdir("work_mem")
for idx in range(num):
with open("work_mem/mem_%02d.v" % idx, "w") as f:
print("""
module top(input clk, i0, i1, i2, i3, output reg o0, o1, o2, o3, o4);
reg [9:0] raddr, waddr, rdata, wdata;
reg [9:0] memory [0:1023];
always @(posedge clk) begin
case ({i0, i1, i2})
0: raddr <= {raddr, i3};
1: waddr <= {waddr, i3};
2: wdata <= {wdata, i3};
3: rdata <= memory[raddr];
4: memory[waddr] <= wdata;
5: rdata <= memory[waddr];
6: {o0, o1, o2, o3, o4} <= rdata[4:0];
7: {o0, o1, o2, o3, o4} <= rdata[9:5];
endcase
end
endmodule
""", file=f)
with open("work_mem/mem_%02d.pcf" % idx, "w") as f:
p = list(np.random.permutation(pins))
for port in [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3", "o4" ]:
print("set_io %s %s" % (port, p.pop()), file=f)
with open("work_mem/Makefile", "w") as f:
print("all: %s" % " ".join(["mem_%02d.bin" % i for i in range(num)]), file=f)
for i in range(num):
print("mem_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh mem_%02d > mem_%02d.log 2>&1 && rm -rf mem_%02d.tmp || tail mem_%02d.log" % (i, i, i, i), file=f)