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Add icefuzz support for the UP5K and rework underlying device specification for more flexibility.

This commit is contained in:
Scott Shawcroft 2017-06-22 17:38:38 -07:00
parent ed8c4e8c03
commit 58a6110be1
20 changed files with 7452 additions and 136 deletions
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77
icefuzz/Makefile
View File

@ -2,8 +2,26 @@ include ../config.mk
export LC_ALL=C
export ICE_SBTIMER_LP=1
#EIGTHK = _8k
THREEH = _384
DEVICECLASS := 1k
ifeq ($(DEVICECLASS), 384)
DEVICE := lp384-cm49
THREEH = _384
endif
ifeq ($(DEVICECLASS), 1k)
DEVICE := hx1k-tq144
endif
ifeq ($(DEVICECLASS), 5k)
DEVICE := up5k-sg48
RAM_SUFFIX := _5k
endif
ifeq ($(DEVICECLASS), 8k)
DEVICE := hx8k-ct256
RAM_SUFFIX = _8k
endif
TESTS =
TESTS += binop
@ -18,32 +36,30 @@ TESTS += gbio
TESTS += gbio2
TESTS += prim
TESTS += fflogic
ifneq ($(THREEH),_384)
ifneq ($(DEVICECLASS),384)
TESTS += ram40
TESTS += mem
TESTS += pll
TESTS += aig
endif
database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(EIGTHK).txt bitdata_ramt$(EIGTHK).txt
ifeq ($(EIGTHK),_8k)
database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt
ifneq ($(RAM_SUFFIX),)
cp cached_ramb.txt bitdata_ramb.txt
cp cached_ramt.txt bitdata_ramt.txt
else
cp cached_ramb_8k.txt bitdata_ramb_8k.txt
cp cached_ramt_8k.txt bitdata_ramt_8k.txt
cp cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt
cp cached_ramt$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt
endif
python3 database.py
ICEDEVICE=$(DEVICECLASS) python3 database.py
python3 export.py
diff -U0 cached_io.txt bitdata_io.txt || cp -v bitdata_io.txt cached_io.txt
diff -U0 cached_logic.txt bitdata_logic.txt || cp -v bitdata_logic.txt cached_logic.txt
diff -U0 cached_ramb.txt bitdata_ramb.txt || cp -v bitdata_ramb.txt cached_ramb.txt
diff -U0 cached_ramt.txt bitdata_ramt.txt || cp -v bitdata_ramt.txt cached_ramt.txt
diff -U0 cached_ramb_8k.txt bitdata_ramb_8k.txt || cp -v bitdata_ramb_8k.txt cached_ramb_8k.txt
diff -U0 cached_ramt_8k.txt bitdata_ramt_8k.txt || cp -v bitdata_ramt_8k.txt cached_ramt_8k.txt
diff -U0 cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt || cp -v bitdata_ramb$(RAM_SUFFIX).txt cached_ramb$(RAM_SUFFIX).txt
diff -U0 cached_ramt$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt || cp -v bitdata_ramt$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt
timings:
ifeq ($(EIGTHK),_8k)
ifeq ($(DEVICECLASS),8k)
cp tmedges.txt tmedges.tmp
set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
@ -52,7 +68,7 @@ ifeq ($(EIGTHK),_8k)
python3 timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new
mv timings_lp8k.new timings_lp8k.txt
else
ifeq ($(THREEH),_384)
ifeq ($(DEVICECLASS),384)
cp tmedges.txt tmedges.tmp
set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
@ -76,11 +92,11 @@ timings_html:
python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html
python3 timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt
gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new
gawk '{ print "ramb$(EIGTHK)", $$0; }' cached_ramb$(EIGTHK).txt >> data_cached.new
gawk '{ print "ramt$(EIGTHK)", $$0; }' cached_ramt$(EIGTHK).txt >> data_cached.new
gawk '{ print "ramb$(RAM_SUFFIX)", $$0; }' cached_ramb$(RAM_SUFFIX).txt >> data_cached.new
gawk '{ print "ramt$(RAM_SUFFIX)", $$0; }' cached_ramt$(RAM_SUFFIX).txt >> data_cached.new
mv data_cached.new data_cached.txt
bitdata_io.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
@ -89,11 +105,11 @@ bitdata_io.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
bitdata_logic.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
grep ^logic $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
bitdata_ramb$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
grep ^ramb$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
bitdata_ramb$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
grep ^ramb$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
bitdata_ramt$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
grep ^ramt$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
grep ^ramt$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS)))
@ -102,21 +118,9 @@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS)))
define data_template
data_$(1).txt: make_$(1).py ../icepack/icepack
ifeq ($(EIGTHK),_8k)
ICE8KPINS=1 python3 make_$(1).py
+ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1)
python3 extract.py -8 work_$(1)/*.glb > $$@
else
ifeq ($(THREEH),_384)
ICE384PINS=1 python3 make_$(1).py
+ICEDEV=lp384-cm49 $(MAKE) -C work_$(1)
python3 extract.py -3 work_$(1)/*.glb > $$@
else
python3 make_$(1).py
+$(MAKE) -C work_$(1)
python3 extract.py work_$(1)/*.glb > $$@
endif
endif
ICEDEVICE=$(DEVICECLASS) python3 make_$(1).py
+ICEDEV=$(DEVICE) $(MAKE) -C work_$(1)
ICEDEVICE=$(DEVICECLASS) python3 extract.py work_$(1)/*.glb > $$@
endef
$(foreach test,$(TESTS),$(eval $(call data_template,$(test))))
@ -141,4 +145,3 @@ clean:
rm -rf timings_*.html
.PHONY: database datafiles check clean

75
icefuzz/cached_io.txt
View File

@ -340,6 +340,19 @@
(14 14) routing glb_netwk_5 <X> wire_io_cluster/io_1/outclk
(14 14) routing glb_netwk_6 <X> wire_io_cluster/io_1/outclk
(14 14) routing glb_netwk_7 <X> wire_io_cluster/io_1/outclk
(14 15) IO control bit: BIODOWN_extra_padeb_test_0
(14 15) IO control bit: BIOUP_extra_padeb_test_0
(14 15) IO control bit: GIODOWN0_extra_padeb_test_0
(14 15) IO control bit: GIODOWN1_extra_padeb_test_0
(14 15) IO control bit: GIOLEFT0_extra_padeb_test_0
(14 15) IO control bit: GIOLEFT1_extra_padeb_test_0
(14 15) IO control bit: GIORIGHT0_extra_padeb_test_0
(14 15) IO control bit: GIORIGHT1_extra_padeb_test_0
(14 15) IO control bit: GIOUP0_extra_padeb_test_0
(14 15) IO control bit: GIOUP1_extra_padeb_test_0
(14 15) IO control bit: HIPBIOUP_extra_padeb_test_0
(14 15) IO control bit: IODOWN_extra_padeb_test_0
(14 15) IO control bit: IOUP_extra_padeb_test_0
(14 2) routing span4_horz_l_13 <X> span4_vert_7
(14 2) routing span4_horz_r_1 <X> span4_vert_7
(14 2) routing span4_vert_b_1 <X> span4_horz_7
@ -388,6 +401,28 @@
(15 11) routing glb_netwk_7 <X> wire_io_cluster/io_1/cen
(15 11) routing lc_trk_g1_2 <X> wire_io_cluster/io_1/cen
(15 11) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/cen
(15 12) IO control bit: BIODOWN_cf_bit_39
(15 12) IO control bit: BIOUP_cf_bit_39
(15 12) IO control bit: GIODOWN0_cf_bit_39
(15 12) IO control bit: GIOLEFT1_cf_bit_39
(15 12) IO control bit: GIORIGHT0_cf_bit_39
(15 12) IO control bit: GIORIGHT1_cf_bit_39
(15 12) IO control bit: GIOUP0_cf_bit_39
(15 12) IO control bit: GIOUP1_cf_bit_39
(15 12) IO control bit: IODOWN_cf_bit_39
(15 14) IO control bit: BIODOWN_extra_padeb_test_1
(15 14) IO control bit: BIOUP_extra_padeb_test_1
(15 14) IO control bit: GIODOWN0_extra_padeb_test_1
(15 14) IO control bit: GIODOWN1_extra_padeb_test_1
(15 14) IO control bit: GIOLEFT0_extra_padeb_test_1
(15 14) IO control bit: GIOLEFT1_extra_padeb_test_1
(15 14) IO control bit: GIORIGHT0_extra_padeb_test_1
(15 14) IO control bit: GIORIGHT1_extra_padeb_test_1
(15 14) IO control bit: GIOUP0_extra_padeb_test_1
(15 14) IO control bit: GIOUP1_extra_padeb_test_1
(15 14) IO control bit: HIPBIOUP_extra_padeb_test_1
(15 14) IO control bit: IODOWN_extra_padeb_test_1
(15 14) IO control bit: IOUP_extra_padeb_test_1
(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_0 wire_io_cluster/io_1/outclk
(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_1 wire_io_cluster/io_1/outclk
(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_2 wire_io_cluster/io_1/outclk
@ -424,6 +459,13 @@
(15 5) routing lc_trk_g1_4 <X> wire_gbuf/in
(15 5) routing lc_trk_g1_6 <X> fabout
(15 5) routing lc_trk_g1_6 <X> wire_gbuf/in
(15 6) IO control bit: BIODOWN_cf_bit_35
(15 6) IO control bit: BIOUP_cf_bit_35
(15 6) IO control bit: GIOLEFT1_cf_bit_35
(15 6) IO control bit: GIORIGHT0_cf_bit_35
(15 6) IO control bit: GIORIGHT1_cf_bit_35
(15 6) IO control bit: GIOUP0_cf_bit_35
(15 6) IO control bit: IODOWN_cf_bit_35
(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_0 wire_io_cluster/io_1/inclk
(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_1 wire_io_cluster/io_1/inclk
(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_2 wire_io_cluster/io_1/inclk
@ -489,7 +531,12 @@
(2 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_1
(2 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_1
(2 0) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_1
(2 0) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_1
(2 0) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_1
(2 0) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_1
(2 0) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_1
(2 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_1
(2 0) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_1
(2 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_1
(2 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_1
(2 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_1
@ -506,6 +553,8 @@
(2 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_4
(2 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_4
(2 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_4
(2 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_4
(2 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_4
(2 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_4
(2 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_4
(2 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_4
@ -518,6 +567,10 @@
(2 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_7
(2 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_7
(2 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_7
(2 4) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_7
(2 4) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_7
(2 4) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_7
(2 4) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_7
(2 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_7
(2 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_7
(2 4) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_7
@ -525,6 +578,7 @@
(2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_34
(2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_34
(2 6) IO control bit: BIODOWN_REN_0
(2 6) IO control bit: BIODOWN_REN_1
(2 6) IO control bit: BIOLEFT_REN_0
(2 6) IO control bit: BIORIGHT_REN_0
(2 6) IO control bit: BIORIGHT_REN_1
@ -563,12 +617,18 @@
(3 0) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_2
(3 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_2
(3 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_2
(3 0) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_2
(3 0) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_2
(3 0) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_2
(3 0) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_2
(3 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_2
(3 0) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_2
(3 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_2
(3 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_2
(3 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_2
(3 0) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_2
(3 0) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_2
(3 1) IO control bit: BIODOWN_REN_0
(3 1) IO control bit: BIODOWN_REN_1
(3 1) IO control bit: BIOLEFT_REN_1
(3 1) IO control bit: BIORIGHT_REN_0
@ -611,6 +671,7 @@
(3 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_5
(3 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_5
(3 2) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_5
(3 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_5
(3 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_5
(3 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_5
(3 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_5
@ -621,7 +682,10 @@
(3 3) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_3
(3 3) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_3
(3 3) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_3
(3 3) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_3
(3 3) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_3
(3 3) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_3
(3 3) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_3
(3 3) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_3
(3 3) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_3
(3 3) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_3
@ -630,6 +694,9 @@
(3 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_8
(3 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_8
(3 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_8
(3 4) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_8
(3 4) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_8
(3 4) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_8
(3 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_8
(3 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_8
(3 4) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_8
@ -637,10 +704,13 @@
(3 5) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_6
(3 5) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_6
(3 5) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_6
(3 5) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_6
(3 5) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_6
(3 5) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_6
(3 5) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_6
(3 5) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_6
(3 5) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_6
(3 6) IO control bit: BIODOWN_IE_0
(3 6) IO control bit: BIODOWN_IE_1
(3 6) IO control bit: BIOLEFT_IE_1
(3 6) IO control bit: BIORIGHT_IE_0
@ -674,11 +744,16 @@
(3 7) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_9
(3 7) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_9
(3 7) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_9
(3 7) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_9
(3 7) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_9
(3 7) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_9
(3 7) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_9
(3 7) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_9
(3 7) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_9
(3 7) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_9
(3 7) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_9
(3 9) IO control bit: BIODOWN_IE_0
(3 9) IO control bit: BIODOWN_IE_1
(3 9) IO control bit: BIOLEFT_IE_0
(3 9) IO control bit: BIORIGHT_IE_0
(3 9) IO control bit: BIORIGHT_IE_1

3578
icefuzz/cached_ramb_5k.txt Normal file
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File diff suppressed because it is too large Load Diff

3637
icefuzz/cached_ramt_5k.txt Normal file
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File diff suppressed because it is too large Load Diff

16
icefuzz/database.py
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@ -2,6 +2,8 @@
import re, sys, os
device_class = os.getenv("ICEDEVICE")
def sort_bits_key(a):
if a[0] == "!": a = a[1:]
return re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a)
@ -136,11 +138,11 @@ with open("database_ramt.txt", "w") as f:
for entry in read_database("bitdata_ramt.txt", "ramt"):
print("\t".join(entry), file=f)
with open("database_ramb_8k.txt", "w") as f:
for entry in read_database("bitdata_ramb_8k.txt", "ramb_8k"):
print("\t".join(entry), file=f)
with open("database_ramt_8k.txt", "w") as f:
for entry in read_database("bitdata_ramt_8k.txt", "ramt_8k"):
print("\t".join(entry), file=f)
if device_class in ["5k", "8k"]:
with open("database_ramb_%s.txt" % (device_class, ), "w") as f:
for entry in read_database("bitdata_ramb_%s.txt" % (device_class, ), "ramb_" + device_class):
print("\t".join(entry), file=f)
with open("database_ramt_8k.txt", "w") as f:
for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class):
print("\t".join(entry), file=f)

10
icefuzz/export.py
View File

@ -1,10 +1,16 @@
#!/usr/bin/env python3
import os
device_class = os.getenv("ICEDEVICE")
with open("../icebox/iceboxdb.py", "w") as f:
for i in [ "database_io", "database_logic", "database_ramb", "database_ramt", "database_ramb_8k", "database_ramt_8k" ]:
files = [ "database_io", "database_logic", "database_ramb", "database_ramt"]
for device_class in ["5k", "8k"]:
files.append("database_ramb_" + device_class)
files.append("database_ramt_" + device_class)
for i in files:
print('%s_txt = """' % i, file=f)
with open("%s.txt" % i, "r") as fi:
for line in fi:
print(line, end="", file=f)
print('"""', file=f)

25
icefuzz/extract.py
View File

@ -1,5 +1,5 @@
#!/usr/bin/env python3
import os
import sys, re
db = set()
@ -9,36 +9,38 @@ mode_384 = False
cur_text_db = None
max_x, max_y = 0, 0
if sys.argv[1] == '-8':
sys.argv = sys.argv[1:]
mode_8k = True
if sys.argv[1] == '-3':
sys.argv = sys.argv[1:]
mode_384 = True
device_class = os.getenv("ICEDEVICE")
for filename in sys.argv[1:]:
with open(filename, "r") as f:
ignore = False
for line in f:
if line == "\n":
pass
elif line.startswith("GlobalNetwork"):
cur_text_db = set()
ignore = False
elif line.startswith("IO"):
match = re.match("IO_Tile_(\d+)_(\d+)", line)
assert match
max_x = max(max_x, int(match.group(1)))
max_y = max(max_y, int(match.group(2)))
cur_text_db = text_db.setdefault("io", set())
ignore = False
elif line.startswith("Logic"):
cur_text_db = text_db.setdefault("logic", set())
ignore = False
elif line.startswith("RAM"):
match = re.match(r"RAM_Tile_\d+_(\d+)", line)
if int(match.group(1)) % 2 == 1:
cur_text_db = text_db.setdefault("ramb_8k" if mode_8k else "ramb", set())
cur_text_db = text_db.setdefault("ramb_" + device_class if device_class in ["5k", "8k"] else "ramb", set())
else:
cur_text_db = text_db.setdefault("ramt_8k" if mode_8k else "ramt", set())
else:
cur_text_db = text_db.setdefault("ramt_" + device_class if device_class in ["5k", "8k"] else "ramt", set())
ignore = False
elif device_class == "5k" and line.startswith(("IpCon", "DSP")):
ignore = True
elif not ignore:
print("'" + line + "'")
assert line.startswith(" ")
cur_text_db.add(line)
@ -60,4 +62,3 @@ for tile_type in text_db:
for line in sorted(db):
print(line)

24
icefuzz/fuzzconfig.py
View File

@ -2,8 +2,11 @@ import os
num = 20
if os.getenv('ICE8KPINS'):
device_class = os.getenv("ICEDEVICE")
if device_class == "8k":
num_ramb40 = 32
num_iobanks = 4
pins="""
A1 A2 A5 A6 A7 A9 A10 A11 A15 A16
@ -26,8 +29,9 @@ if os.getenv('ICE8KPINS'):
gpins = "C8 F7 G1 H11 H16 I3 K9 R9".split()
elif os.getenv('ICE384PINS'):
elif device_class == "384":
num_ramb40 = 0
num_iobanks = 3
pins = """
A1 A2 A3 A4 A5 A6 A7
@ -41,8 +45,9 @@ elif os.getenv('ICE384PINS'):
gpins = "B4 C4 D2 D6 D7 E2 F3 F4".split()
else:
elif device_class == "1k":
num_ramb40 = 16
num_iobanks = 4
pins = """
1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34
@ -52,4 +57,17 @@ else:
""".split()
gpins = "20 21 49 50 93 94 128 129".split()
elif device_class == "5k":
num_ramb40 = 30
num_iobanks = 2
#TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason.
# Also add 14 15 16 17 which are constrained to SPI.
pins = """2 3 4 6 9 10 11 12
13 18 19 20 21 23
25 26 27 28 31 32 34 35 36
37 38 42 43 44 45 46 47 48
""".split()
#TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason.
gpins = "20 35 37 44".split()

4
icefuzz/icecube.sh
View File

@ -56,6 +56,8 @@ if [ "$1" == "-up5k" ]; then
shift
fi
ICECUBEDIR=~/lscc/iCEcube2.2017.01
set -ex
set -- ${1%.v}
icecubedir="${ICECUBEDIR:-/opt/lscc/iCEcube2.2015.08}"
@ -417,4 +419,4 @@ if [ -n "$ICE_SBTIMER_LP" ]; then
fi
export LD_LIBRARY_PATH=""
$scriptdir/../icepack/iceunpack "$1.bin" "$1.asc"
$scriptdir/../icepack/iceunpack -vv "$1.bin" "$1.asc"

13
icefuzz/make_aig.py
View File

@ -7,11 +7,13 @@ import os
os.system("rm -rf work_aig")
os.mkdir("work_aig")
w = len(pins) // 2
for idx in range(num):
with open("work_aig/aig_%02d.v" % idx, "w") as f:
print("module top(input [31:0] a, output [31:0] y);", file=f)
print("module top(input [%d:0] a, output [%d:0] y);" % (w-1, w-1), file=f)
sigs = ["a[%d]" % i for i in range(32)]
sigs = ["a[%d]" % i for i in range(w)]
netidx = 0
for i in range(100 if num_ramb40 < 20 else 1000):
@ -40,20 +42,19 @@ for idx in range(num):
sigs.append(newnet)
for i in range(32):
for i in range(w):
print(" assign y[%d] = %s;" % (i, sigs[i]), file=f)
print("endmodule", file=f)
with open("work_aig/aig_%02d.pcf" % idx, "w") as f:
p = np.random.permutation(pins)
for i in range(32):
for i in range(w):
print("set_io a[%d] %s" % (i, p[i]), file=f)
print("set_io y[%d] %s" % (i, p[i+32]), file=f)
print("set_io y[%d] %s" % (i, p[i+w]), file=f)
with open("work_aig/Makefile", "w") as f:
print("all: %s" % " ".join(["aig_%02d.bin" % i for i in range(num)]), file=f)
for i in range(num):
print("aig_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh aig_%02d > aig_%02d.log 2>&1 && rm -rf aig_%02d.tmp || tail aig_%02d.log" % (i, i, i, i), file=f)

18
icefuzz/make_fanout.py
View File

@ -7,26 +7,22 @@ import os
os.system("rm -rf work_fanout")
os.mkdir("work_fanout")
for idx in range(num):
output_count = len(pins) - 2
with open("work_fanout/fanout_%02d.v" % idx, "w") as f:
if os.getenv('ICE384PINS'):
print("module top(input [1:0] a, output [33:0] y);", file=f)
print(" assign y = {8{a}};", file=f)
else:
print("module top(input [1:0] a, output [63:0] y);", file=f)
print(" assign y = {32{a}};", file=f)
print("module top(input [1:0] a, output [%d:0] y);" % (output_count,), file=f)
print(" assign y = {%d{a}};" % (output_count,), file=f)
print("endmodule", file=f)
with open("work_fanout/fanout_%02d.pcf" % idx, "w") as f:
p = np.random.permutation(pins)
r = 34 if os.getenv('ICE384PINS') else 64
for i in range(r):
for i in range(output_count):
print("set_io y[%d] %s" % (i, p[i]), file=f)
print("set_io a[0] %s" % p[r], file=f)
print("set_io a[1] %s" % p[r+1], file=f)
print("set_io a[0] %s" % p[output_count], file=f)
print("set_io a[1] %s" % p[output_count+1], file=f)
with open("work_fanout/Makefile", "w") as f:
print("all: %s" % " ".join(["fanout_%02d.bin" % i for i in range(num)]), file=f)
for i in range(num):
print("fanout_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh fanout_%02d > fanout_%02d.log 2>&1 && rm -rf fanout_%02d.tmp || tail fanout_%02d.log" % (i, i, i, i), file=f)

11
icefuzz/make_fflogic.py
View File

@ -7,6 +7,8 @@ import os
os.system("rm -rf work_fflogic")
os.mkdir("work_fflogic")
w = (len(pins) - 4) // 5
def random_op():
return np.random.choice(["+", "-", "*", "^", "&", "|"])
@ -37,12 +39,8 @@ def print_seq_op(dst, src1, src2, op, f):
for idx in range(num):
with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f:
if os.getenv('ICE384PINS'):
print("module top(input clk, rst, en, input [4:0] a, b, c, d, output [4:0] y, output z);", file=f)
print(" reg [4:0] p, q;", file=f)
else:
print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f)
print(" reg [15:0] p, q;", file=f)
print("module top(input clk, rst, en, input [%d:0] a, b, c, d, output [%d:0] y, output z);" % (w-1, w-1), file=f)
print(" reg [%d:0] p, q;" % (w-1,), file=f)
print_seq_op("p", "a", "b", random_op(), f)
print_seq_op("q", "c", "d", random_op(), f)
@ -54,4 +52,3 @@ with open("work_fflogic/Makefile", "w") as f:
for i in range(num):
print("fflogic_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh fflogic_%02d > fflogic_%02d.log 2>&1 && rm -rf fflogic_%02d.tmp || tail fflogic_%02d.log" % (i, i, i, i), file=f)

24
icefuzz/make_gbio.py
View File

@ -7,14 +7,26 @@ import os
os.system("rm -rf work_gbio")
os.mkdir("work_gbio")
w = 4 if os.getenv('ICE384PINS') else 8
device_class = os.getenv("ICEDEVICE")
for p in gpins:
if p in pins: pins.remove(p)
# We can either tickle every global buffer or we don't have enough pins to do
# the full logic for each one.
w = min(min((len(pins) - 8) // 4, len(gpins)), 8)
for idx in range(num):
with open("work_gbio/gbio_%02d.v" % idx, "w") as f:
glbs = np.random.permutation(list(range(8)))
if w <= 4:
din_0 = (w - 2, w)
else:
din_0 = (4, "%d:4" % (w - 1,))
din_0 = np.random.choice(["din_0", "{din_0[%d:0], din_0[%s]}" % din_0])
din_1 = np.random.choice(["din_1", "{din_1[1:0], din_1[%d:2]}" % (w - 1,)])
globals_0 = np.random.choice(["globals", "{globals[0], globals[%d:1]}" % (w - 1, )])
print("""
module top (
inout [%s:0] pin,
@ -64,12 +76,9 @@ for idx in range(num):
np.random.choice(["oen", "globals", "din_0+din_1", "din_0^din_1"]),
np.random.choice(["dout_1", "globals", "globals^dout_0", "din_0+din_1", "~din_0"]),
np.random.choice(["dout_0", "globals", "globals^dout_1", "din_0+din_1", "~din_1"]),
np.random.choice(["din_0", "{din_0[2:0], din_0[3]}"]) if os.getenv('ICE384PINS')
else np.random.choice(["din_0", "{din_0[3:0], din_0[7:4]}"]) ,
np.random.choice(["din_1", "{din_1[1:0], din_1[3:2]}"]) if os.getenv('ICE384PINS')
else np.random.choice(["din_1", "{din_1[1:0], din_1[7:2]}"]),
np.random.choice(["globals", "{globals[0], globals[3:1]}"]) if os.getenv('ICE384PINS')
else np.random.choice(["globals", "{globals[0], globals[7:1]}"]),
din_0,
din_1,
globals_0,
glbs[0], glbs[1], glbs[1], glbs[2], glbs[3]
), file=f)
with open("work_gbio/gbio_%02d.pcf" % idx, "w") as f:
@ -89,4 +98,3 @@ with open("work_gbio/Makefile", "w") as f:
for i in range(num):
print("gbio_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh gbio_%02d > gbio_%02d.log 2>&1 && rm -rf gbio_%02d.tmp || tail gbio_%02d.log" % (i, i, i, i), file=f)

7
icefuzz/make_gbio2.py
View File

@ -7,11 +7,13 @@ import os
os.system("rm -rf work_gbio2")
os.mkdir("work_gbio2")
w = 4 if os.getenv('ICE384PINS') else 8
for p in gpins:
if p in pins: pins.remove(p)
# We can either tickle every global buffer or we don't have enough pins to do
# the full logic for each one.
w = min(min((len(pins) - 8) // 4, len(gpins)), 8)
for idx in range(num):
with open("work_gbio2/gbio2_%02d.v" % idx, "w") as f:
glbs = np.random.permutation(list(range(8)))
@ -86,4 +88,3 @@ with open("work_gbio2/Makefile", "w") as f:
for i in range(num):
print("gbio2_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh gbio2_%02d > gbio2_%02d.log 2>&1 && rm -rf gbio2_%02d.tmp || tail gbio2_%02d.log" % (i, i, i, i), file=f)

4
icefuzz/make_io.py
View File

@ -7,8 +7,7 @@ import os
os.system("rm -rf work_io")
os.mkdir("work_io")
if os.getenv('ICE384PINS'): w = 3
else: w = 4
w = num_iobanks
for idx in range(num):
with open("work_io/io_%02d.v" % idx, "w") as f:
@ -60,4 +59,3 @@ with open("work_io/Makefile", "w") as f:
for i in range(num):
print("io_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh io_%02d > io_%02d.log 2>&1 && rm -rf io_%02d.tmp || tail io_%02d.log" % (i, i, i, i), file=f)

18
icefuzz/make_logic.py
View File

@ -11,26 +11,22 @@ def random_op():
return np.random.choice(["+", "-", "^", "&", "|", "&~", "|~"])
for idx in range(num):
bus_width = len(pins) // 5
with open("work_logic/logic_%02d.v" % idx, "w") as f:
if os.getenv('ICE384PINS'):
print("module top(input [5:0] a, b, c, d, output [5:0] y);", file=f)
else:
print("module top(input [15:0] a, b, c, d, output [15:0] y);", file=f)
print("module top(input [%d:0] a, b, c, d, output [%d:0] y);" % (bus_width, bus_width), file=f)
print(" assign y = (a %s b) %s (c %s d);" % (random_op(), random_op(), random_op()), file=f)
print("endmodule", file=f)
with open("work_logic/logic_%02d.pcf" % idx, "w") as f:
p = np.random.permutation(pins)
r = 6 if os.getenv('ICE384PINS') else 16
for i in range(r):
for i in range(bus_width):
print("set_io a[%d] %s" % (i, p[i]), file=f)
print("set_io b[%d] %s" % (i, p[i+r]), file=f)
print("set_io c[%d] %s" % (i, p[i+r*2]), file=f)
print("set_io d[%d] %s" % (i, p[i+r*3]), file=f)
print("set_io y[%d] %s" % (i, p[i+r*4]), file=f)
print("set_io b[%d] %s" % (i, p[i+bus_width]), file=f)
print("set_io c[%d] %s" % (i, p[i+bus_width*2]), file=f)
print("set_io d[%d] %s" % (i, p[i+bus_width*3]), file=f)
print("set_io y[%d] %s" % (i, p[i+bus_width*4]), file=f)
with open("work_logic/Makefile", "w") as f:
print("all: %s" % " ".join(["logic_%02d.bin" % i for i in range(num)]), file=f)
for i in range(num):
print("logic_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh logic_%02d > logic_%02d.log 2>&1 && rm -rf logic_%02d.tmp || tail logic_%02d.log" % (i, i, i, i), file=f)

19
icefuzz/make_mesh.py
View File

@ -7,26 +7,25 @@ import os
os.system("rm -rf work_mesh")
os.mkdir("work_mesh")
# This test maps a random set of pins to another random set of outputs.
device_class = os.getenv("ICEDEVICE")
for idx in range(num):
io_count = len(pins) // 2
with open("work_mesh/mesh_%02d.v" % idx, "w") as f:
if os.getenv('ICE384PINS'):
print("module top(input [13:0] a, output [13:0] y);", file=f)
else:
print("module top(input [39:0] a, output [39:0] y);", file=f)
print("module top(input [%d:0] a, output [%d:0] y);" % (io_count, io_count), file=f)
print(" assign y = a;", file=f)
print("endmodule", file=f)
with open("work_mesh/mesh_%02d.pcf" % idx, "w") as f:
p = np.random.permutation(pins)
if os.getenv('ICE384PINS'): r = 14
else: r = 40
for i in range(r):
for i in range(io_count):
print("set_io a[%d] %s" % (i, p[i]), file=f)
for i in range(r):
print("set_io y[%d] %s" % (i, p[r+i]), file=f)
for i in range(io_count):
print("set_io y[%d] %s" % (i, p[io_count+i]), file=f)
with open("work_mesh/Makefile", "w") as f:
print("all: %s" % " ".join(["mesh_%02d.bin" % i for i in range(num)]), file=f)
for i in range(num):
print("mesh_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh mesh_%02d > mesh_%02d.log 2>&1 && rm -rf mesh_%02d.tmp || tail mesh_%02d.log" % (i, i, i, i), file=f)

3
icefuzz/make_prim.py
View File

@ -7,7 +7,7 @@ import os
os.system("rm -rf work_prim")
os.mkdir("work_prim")
w = 10 if os.getenv('ICE384PINS') else 24
w = len(pins) // 4
for idx in range(num):
with open("work_prim/prim_%02d.v" % idx, "w") as f:
@ -48,4 +48,3 @@ with open("work_prim/Makefile", "w") as f:
for i in range(num):
print("prim_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh prim_%02d > prim_%02d.log 2>&1 && rm -rf prim_%02d.tmp || tail prim_%02d.log" % (i, i, i, i), file=f)

9
icefuzz/make_ram40.py
View File

@ -9,12 +9,12 @@ os.mkdir("work_ram40")
for idx in range(num):
with open("work_ram40/ram40_%02d.v" % idx, "w") as f:
glbs = ["glb[%d]" % i for i in range(np.random.randint(9))]
glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)]
glbs_choice = ["wa", "ra", "msk", "wd", "we", "wce", "wc", "re", "rce", "rc"]
print("""
module top (
input [%d:0] glb_pins,
input [59:0] in_pins,
input [%d:0] in_pins,
output [15:0] out_pins
);
wire [%d:0] glb, glb_pins;
@ -22,7 +22,7 @@ for idx in range(num):
.USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins),
.GLOBAL_BUFFER_OUTPUT(glb)
);
""" % (len(glbs)-1, len(glbs)-1, len(glbs)-1), file=f)
""" % (len(glbs)-1, len(pins) - 16 - 1, len(glbs)-1, len(glbs)-1), file=f)
bits = ["in_pins[%d]" % i for i in range(60)]
bits = list(np.random.permutation(bits))
for i in range(num_ramb40):
@ -98,7 +98,7 @@ for idx in range(num):
print("endmodule", file=f)
with open("work_ram40/ram40_%02d.pcf" % idx, "w") as f:
p = list(np.random.permutation(pins))
for i in range(60):
for i in range(len(pins) - 16):
print("set_io in_pins[%d] %s" % (i, p.pop()), file=f)
for i in range(16):
print("set_io out_pins[%d] %s" % (i, p.pop()), file=f)
@ -108,4 +108,3 @@ with open("work_ram40/Makefile", "w") as f:
for i in range(num):
print("ram40_%02d.bin:" % i, file=f)
print("\t-bash ../icecube.sh ram40_%02d > ram40_%02d.log 2>&1 && rm -rf ram40_%02d.tmp || tail ram40_%02d.log" % (i, i, i, i), file=f)

16
icepack/icepack.cc
View File

@ -170,7 +170,7 @@ struct BramIndexConverter
int bank_off;
BramIndexConverter(const FpgaConfig *fpga, int tile_x, int tile_y);
void get_bram_index(uint bit_x, uint bit_y, uint &bram_bank, uint &bram_x, uint &bram_y) const;
void get_bram_index(int bit_x, int bit_y, int &bram_bank, int &bram_x, int &bram_y) const;
};
static void update_crc16(uint16_t &crc, uint8_t byte)
@ -712,7 +712,7 @@ void FpgaConfig::read_ascii(std::istream &ifs)
for (int i = 0; i < 4; i++)
if ((value & (1 << i)) != 0) {
uint bram_bank, bram_x, bram_y;
int bram_bank, bram_x, bram_y;
bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y);
this->bram[bram_bank][bram_x][bram_y] = true;
}
@ -793,17 +793,17 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const
BramIndexConverter bic(this, x, y);
ofs << stringf(".ram_data %d %d\n", x, y);
for (uint bit_y = 0; bit_y < 16; bit_y++) {
for (uint bit_x = 256-4; bit_x > 0; bit_x -= 4) {
for (int bit_y = 0; bit_y < 16; bit_y++) {
for (int bit_x = 256-4; bit_x >= 0; bit_x -= 4) {
int value = 0;
for (int i = 0; i < 4; i++) {
uint bram_bank, bram_x, bram_y;
int bram_bank, bram_x, bram_y;
bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y);
if (bram_x >= this->bram[bram_bank].size()) {
if (bram_x >= int(this->bram[bram_bank].size())) {
error("bram_x %u higher than loaded bram size %lu\n", bram_x, this->bram[bram_bank].size());
break;
}
if (bram_y >= this->bram[bram_bank][bram_x].size()) {
if (bram_y >= int(this->bram[bram_bank][bram_x].size())) {
error("bram_y %u higher than loaded bram size %lu\n", bram_y, this->bram[bram_bank][bram_x].size());
break;
}
@ -1094,7 +1094,7 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
this->bank_off = 16 * (y_offset / 2);
}
void BramIndexConverter::get_bram_index(uint bit_x, uint bit_y, uint &bram_bank, uint &bram_x, uint &bram_y) const
void BramIndexConverter::get_bram_index(int bit_x, int bit_y, int &bram_bank, int &bram_x, int &bram_y) const
{
int index = 256 * bit_y + (16*(bit_x/16) + 15 - bit_x%16);
bram_bank = bank_num;