From cfc6e9fdf70e0c788ad12b7f58237b02deb9d1e1 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 20 Mar 2023 09:12:23 +0100 Subject: [PATCH] Update BRAM NegClk info based on latest testing Signed-off-by: gatecat --- docs/ram_tile.html | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/ram_tile.html b/docs/ram_tile.html index 73bda8d..2264966 100644 --- a/docs/ram_tile.html +++ b/docs/ram_tile.html @@ -91,8 +91,8 @@ The read/write mode selects the width of the read/write port:

-The NegClk bit in the RAMB tile negates the polarity of the WCLK port, -and the NegClk bit in the RAMT tile negates the polarity of the RCLK port. +The NegClk bit in the RAMB tile (1k die) or RAMT tile (other devices) negates the polarity of the WCLK port, +and the NegClk bit in the RAMT (1k die) or RAMB tile (other devices) tile negates the polarity of the RCLK port.