<p>The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described as<spanstyle="font-family:monospace">CBIT[24:0]</span>. For most DSP tiles,
these follow a logical order where <spanstyle="font-family:monospace">CBIT[7:0]</span> maps to DSP0 <spanstyle="font-family:monospace">CBIT[7:0]</span>; <spanstyle="font-family:monospace">CBIT[15:8]</span>
to DSP1 <spanstyle="font-family:monospace">CBIT[7:0]</span>, <spanstyle="font-family:monospace">CBIT[23:16]</span> to DSP2 <spanstyle="font-family:monospace">CBIT[7:0]</span>
and <spanstyle="font-family:monospace">CBIT[24]</span> to DSP3 <spanstyle="font-family:monospace">CBIT0</span>.
<p>However, there is one location where configuration bits are swapped between DSP tiles and IPConnect tiles. In DSP1 (0, 16) <spanstyle="font-family:monospace">CBIT[4:1]</span> are used
for IP such as the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) <spanstyle="font-family:monospace">CBIT[6:3]</span>.</p>
<p>The full list of configuration bits, including the changes for the DSP at (0, 15) are described in the table below.</p>
All active DSP tiles, and all IPConnect tiles whether used or not, have some bits set which reflect their logic tile heritage. The <spanstyle="font-family:monospace">LC_<em>x</em></span>
bits which would be used to configure the logic cell, are set to the below pattern for each "logic cell" (interpreting them like a logic tile):<br/>
Coincidentally or not, this corresponds to a buffer passing through input 2 to the output. For each "cell" the cascade bit <spanstyle="font-family:monospace">LC0<em>x</em>_inmux02_5</span> is
also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. It is not yet known if this serves any purpose, or is merely a remainder of Lattice's
internal testing.
</p>
</p>
<h2>IPConnect Tiles</h2>
<p>IPConnect tiles are used for connections to all of the other UltraPlus features, such as I2C/SPI, SPRAM, RGB and oscillators. Like DSP tiles,
they are structually similar to logic tiles. The outputs of IP functions are connected to nets named <spanstyle="font-family:monospace">slf_op_0</span> through <spanstyle="font-family:monospace">slf_op_7</span>,
and the inputs use the LUT/FF inputs in the same way as DSP tiles.</p>
<h2>Internal Oscillators</h2>
Both of the internal oscillators are connected through IPConnect tiles, with their outputs optionally connected to the global networks,
by setting the "padin" extra bit (the used global networks 4 and 5 don't have physical pins on UltraPlus devices).
and the <spanstyle="font-family:monospace">CLKHFEN</span> input connects through input <spanstyle="font-family:monospace">lutff_7/in_3</span> of the same tile.<br/>
The <spanstyle="font-family:monospace">CLKHF</span> output of SB_HFOSC is connected to both IPConnect tile (0, 28) output <spanstyle="font-family:monospace">slf_op_7</span> and to the <spanstyle="font-family:monospace">padin</span>
of <spanstyle="font-family:monospace">glb_netwk_4</span>.</p>
<p>Configuration bit <spanstyle="font-family:monospace">CLKHF_DIV[1]</span> maps to DSP1 tile (0, 16) config bit <spanstyle="font-family:monospace">CBIT_4</span>, and
<spanstyle="font-family:monospace">CLKHF_DIV[0]</span> maps to DSP1 tile (0, 16) config bit <spanstyle="font-family:monospace">CBIT_3</span>.</p>
and the <spanstyle="font-family:monospace">CLKLFEN</span> input connects through input <spanstyle="font-family:monospace">lutff_7/in_3</span> of the same tile.<br/>
The <spanstyle="font-family:monospace">CLKLF</span> output of SB_LFOSC is connected to both IPConnect tile (25, 29) output <spanstyle="font-family:monospace">slf_op_0</span> and to the <spanstyle="font-family:monospace">padin</span>
of <spanstyle="font-family:monospace">glb_netwk_5</span>.</p>
<p>The UltraPlus devices have 1Mbit of extra single-ported RAM, split into 4 256kbit blocks. The full list of connections for each SPRAM block in the 5k device is shown below,
as well as the location of the 1 configuration bit which is set to enable use of that SPRAM block.</p>
<p>The UltraPlus devices contain an internal 3-channel 2-24mA constant-current driver intended for RGB led driving (SB_RGBA_DRV). It is broken out onto 3 pins: 39, 40 and 41 on the QFN48 package.
The LED driver is implemented using the IPConnect tiles and is entirely seperate to the IO cells, if the LED driver is ignored or disabled on a pin then the pin
can be used as an open-drain IO using the standard IO cell.</p>
<p>Note that the UltraPlus devices also have a seperate PWM generator IP core, which would often be connected to this one to create LED effects such as "breathing" without
involving FPGA resources.</p>
<p>The LED driver connections are shown in the label below.</p>
