Alan Mishchenko e63c603e92 Fixing assert which failes when SAT solver returns after a timeout.

2012-08-31 00:52:08 -07:00

..

aig

Fixing assert which failes when SAT solver returns after a timeout.

2012-08-31 00:52:08 -07:00

base

Fixing the way constants are written into mapped Verilog files.

2012-08-31 00:05:10 -07:00

bdd

Compiler warnings.

2012-08-29 17:31:14 -07:00

bool

Added new algorithm for NPN semi-canonical form computation.

2012-08-23 22:20:27 -07:00

map

Improvements to gate-sizing.

2012-08-30 21:46:31 -07:00

misc

Added printout of library cells.

2012-08-27 19:58:15 -07:00

opt

Added an API to convert a multi-output PLA into a shared AIG.

2012-08-29 12:43:55 -07:00

phys/place

Major restructuring of the code.

2012-01-21 04:30:10 -08:00

proof

Compiler warnings.

2012-08-26 09:31:43 -07:00

python

Updated Python code to reflect change in include files.

2012-07-09 17:04:10 -07:00

sat

Bug fix in &gla.

2012-08-27 13:49:53 -07:00

demo.c

Fixing time primtouts throughout the code.

2012-07-07 18:15:08 -07:00

generic.c

initial commit of public abc

2010-11-01 01:35:04 -07:00

generic.h

Major restructuring of the code.

2012-01-21 04:30:10 -08:00

starter.c

Adding simple program for executing several instances of ABC in parallel.

2012-07-07 20:37:16 -07:00

template.c

Major restructuring of the code.

2012-01-21 04:30:10 -08:00