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2,945 Commits 27 Branches 57 Tags 58 MiB
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38 Commits

Author SHA1 Message Date
Alan Mishchenko aadfea8b4d Integrating barrier buffers. 2014-12-13 12:37:04 -08:00
Alan Mishchenko 93bec213fc Bug fix in timing update. 2013-11-26 01:03:53 -08:00
Alan Mishchenko e70adbcd2d Improvements to the standard cell flow. 2013-11-08 15:16:13 -08:00
Alan Mishchenko 24ffd5269a Organizing the timing report functions. 2013-11-07 11:26:40 -08:00
Alan Mishchenko 4774dc56fe Fixing the wire-load approximation problem. 2013-11-07 10:24:47 -08:00
Alan Mishchenko 1692c1a57a Improvements to buffering and sizing. 2013-10-13 23:08:52 -07:00
Alan Mishchenko a4f80c1d36 Cleaning up buffering code. 2013-10-13 21:05:35 -07:00
Alan Mishchenko 89cab3adec Normalization of slew/load values. 2013-10-13 20:55:24 -07:00
Alan Mishchenko 7b99370e0a Changing default values. 2013-10-02 14:36:33 -07:00
Alan Mishchenko 3d8dc1217c Integrating input driving cell constraint into buffering/sizing. 2013-09-17 23:00:59 -07:00
Alan Mishchenko a2d97cf2b6 Debugging and finetuning the flow. 2013-09-17 16:43:42 -07:00
Alan Mishchenko 73a997a8bd Adding commands to set and print timing constraints. 2013-09-17 14:47:34 -07:00
Alan Mishchenko ae27704c13 Integrated buffering and sizing. 2013-08-11 11:35:22 -07:00
Alan Mishchenko ec4804aab6 Integrated buffering and sizing. 2013-08-11 00:49:34 -07:00
Alan Mishchenko 6c4252c5c9 Integrated buffering and sizing. 2013-08-10 18:11:09 -07:00
Alan Mishchenko 573d6d7ab7 Enable wire load estimation in buffering/sizing. 2013-08-10 10:27:55 -07:00
Alan Mishchenko 6e2ee1d30a Integrated buffering and sizing. 2013-08-09 22:13:13 -07:00
Alan Mishchenko 4af5587cbf Integrated buffering and sizing. 2013-08-09 21:44:18 -07:00
Alan Mishchenko fbdaf2075f Integrated buffering and sizing. 2013-08-09 21:05:06 -07:00
Alan Mishchenko d4ad3b4156 Improvements to buffering and sizing. 2013-08-09 19:47:58 -07:00
Alan Mishchenko 633db0f4ad Improvements to buffering and sizing. 2013-08-09 17:54:18 -07:00
Alan Mishchenko b98345ced5 Improvements to buffering and sizing. 2013-08-09 12:36:48 -07:00
Alan Mishchenko 95684b044a Improvements to buffering and sizing. 2013-08-09 11:15:20 -07:00
Alan Mishchenko 881b2ec46f Integrated buffering and sizing. 2013-08-08 18:23:00 -07:00
Alan Mishchenko 655dc4e727 Improvements to buffering and sizing. 2013-08-07 12:32:33 -07:00
Alan Mishchenko 8576e4b440 Improvements to buffering and sizing. 2013-08-06 22:51:39 -07:00
Alan Mishchenko 7a6f335ea6 Improvements to buffering and sizing. 2013-08-06 12:22:13 -07:00
Alan Mishchenko 1a55882ad9 Adding new (un)buffering with phase information. 2013-08-05 18:33:38 -07:00
Alan Mishchenko 1558fe6110 Adding code to estimate buffer trees. 2013-08-05 10:45:06 -07:00
Alan Mishchenko 9d19598162 Change from input slew to input drive strength in the BLIF file. 2013-08-04 12:19:24 -07:00
Alan Mishchenko 56a233be91 Adding switch 'buffer -p' to enable buffing of the primary inputs. 2013-08-02 23:23:45 -07:00
Alan Mishchenko f09a704250 Added commands 'maxsize' and 'unbuffer'. 2013-07-29 21:01:05 -07:00
Alan Mishchenko 1dca7458f3 Improved buffering. 2013-07-29 18:55:13 -07:00
Alan Mishchenko 4c6804c3ae Improved gate-sizing. 2013-07-29 10:10:21 -07:00
Alan Mishchenko 00d023713b Tuning standard-cell mapping flow. 2013-07-24 09:54:53 -07:00
Alan Mishchenko 84c0b9d69b Tuning standard-cell mapping flow. 2013-07-23 16:15:03 -07:00
Alan Mishchenko f392645daf Generating GENLIB library from SCL. 2013-07-22 13:25:51 -07:00
Alan Mishchenko fd28deefc7 Restructuring gate-sizing code trying to separate timing analysis. 2013-07-21 17:55:15 -07:00