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5119 Commits

Author SHA1 Message Date
Alan Mishchenko 683882f2bb Experiments with stochastic synthesis. 2023-07-22 22:18:28 -07:00
Alan Mishchenko 0108175c6c Bug fix in 'dsd'. 2023-07-22 17:08:01 -07:00
Alan Mishchenko a620c09c40 Adding functional comparison to &compare. 2023-07-22 16:44:33 -07:00
phsauter 0f7d05d531 fix Segfault in retime command 2023-07-22 21:20:09 +02:00
Alan Mishchenko 3592078ddb Partitioned &scorr. 2023-07-21 18:49:06 -07:00
Alan Mishchenko 55ed1e6698 Changing command &permute to generate random NPNP transformations. 2023-07-21 16:15:34 -07:00
Alan Mishchenko 623d0f3c9f Change in how signal names are printing in 'print_level'. 2023-07-18 21:00:13 -07:00
Alan Mishchenko 0828ac28a0 Bug fix in Verilog writer. 2023-07-18 15:53:20 -07:00
alanminko 354d302fef
Merge pull request #231 from salfter/c++17-fix 
fix errors when compiling within Yosys: "ISO C++17 does not allow 'register' storage class specifier"
 2023-07-18 11:33:57 -07:00
Scott Alfter 927b60b7a0 fix errors when compiling within Yosys: "ISO C++17 does not allow 'register' storage class specifier" 2023-07-18 09:17:58 -07:00
Alan Mishchenko 59cfcd2240 Compiler warnings. 2023-07-18 09:00:11 -07:00
Cunxi Yu 5bb7fb76a7 add orchestration function (local greedy); usage: orchestrate -h 2023-07-16 12:20:10 -06:00
Alan Mishchenko 766f64e221 Updating 'sim' command to print input patterns. 2023-07-14 20:23:56 -07:00
Alan Mishchenko c70de10002 Updating &saveaig command. 2023-07-14 20:06:22 -07:00
Alan Mishchenko e61194bbed Bug fix. 2023-07-08 10:18:18 -07:00
Alan Mishchenko a82bbaa91d Bug fix in equiv class filtering. 2023-07-07 14:03:35 -07:00
Alan Mishchenko 373c5eccf3 Experiment with multipliers. 2023-07-07 13:12:22 -07:00
Jannis Harder 1bd088d027 fold: Option (-s) to make sequential cleanup optional 2023-06-28 10:28:24 +02:00
Rajit Manohar 62b85322ea no need to call strlen on a constant 2023-06-24 12:34:24 -04:00
Rajit Manohar bbdfe37bf9 fix segv when obj is a primary input 2023-06-24 12:17:57 -04:00
Miodrag Milanovic 1de4eafb0d fix segfault 2023-06-06 13:59:30 +02:00
Miodrag Milanovic 0b361354b3 Merge remote-tracking branch 'origin/master' into yosys-experimental 2023-06-06 11:55:17 +02:00
alanminko a5a6254db1
Merge pull request #173 from mmicko/namespace_fix 
Prevent types from stdint to be defined under abc namespace
 2023-05-19 18:15:09 -07:00
alanminko cf25d25dd0
Merge pull request #195 from hzeller/20221121-fix-msan-issue 
Make sure all 32 bits of bit-field are initialized.
 2023-05-18 22:33:14 -07:00
alanminko ea40a95830
Merge pull request #196 from hzeller/20221121-fix-ub 
Fix undefined behavior in signed/unsigned shifting.
 2023-05-18 22:33:01 -07:00
alanminko 4f0cdd2167
Merge pull request #217 from hzeller/20230427-avoid-double-define 
Don't #define _DEFAULT_SOURCE if already defined.
 2023-05-18 22:32:48 -07:00
alanminko 80c1c01641
Merge pull request #225 from hzeller/20230515-fully-qualify-inserter 
Fully namespace-qualify std::inserter(); add missing include.
 2023-05-18 22:32:35 -07:00
Alan Mishchenko 5a9a902044 Bug fix in equivalence class handling (another try). 2023-05-17 10:34:14 -07:00
Henner Zeller ed7de06726 Fully namespace-qualify std::inserter(); add missing include. 
Signed-off-by: Henner Zeller <hzeller@google.com>
 2023-05-15 09:14:40 -07:00
alanminko 3d35624be6
Merge pull request #224 from MyskYko/transduction 
Transduction option fix and multi-threading
 2023-05-14 14:12:26 -07:00
Yukio Miyasaka 16894c56ee thread parallelism 2023-05-14 13:48:40 -07:00
Alan Mishchenko 96e1de436e Bug fix in equivalence class handling (another try). 2023-05-14 12:43:07 -07:00
Alan Mishchenko bb4378934d Removing a global variable in resub. 2023-05-13 13:53:59 -07:00
Yukio Miyasaka 3af039d7c3 zero cost hop 2023-05-12 22:10:40 -07:00
Yukio Miyasaka a3fb930e44 fix option 2023-05-12 21:44:29 -07:00
Alan Mishchenko 7e501b9b02 Bug fix in equivalence class handling. 2023-05-12 18:39:47 -07:00
alanminko 41a2b2a0ef
Merge pull request #223 from MyskYko/transduction 
transtoch with exdc
 2023-05-12 12:36:05 -07:00
MyskYko 1f16d8bc90 transtoch with exdc 2023-05-12 12:15:23 -07:00
Alan Mishchenko 26edc73b04 Bug fix in miter generation. 2023-05-11 19:20:27 -07:00
Alan Mishchenko 2c9937e0dd Small bug in managing AIG manager name. 2023-05-10 15:05:08 -07:00
Alan Mishchenko 7c04730a24 A minor change and adding ABC file markers. 2023-05-10 12:20:15 -07:00
alanminko 233680f286
Merge pull request #220 from MyskYko/transduction 
Stochastic Transduction Script
 2023-05-10 12:09:45 -07:00
MyskYko 36b357175a stochastic script for transduction 2023-05-06 04:15:34 -07:00
Alan Mishchenko 875ef73275 Temporarily disabling &transduction for an old windows compiler. 2023-05-04 12:27:08 -07:00
alanminko 38cd47b46c
Merge pull request #219 from MyskYko/transduction 
Transduction method
 2023-05-04 14:20:34 -04:00
MyskYko 3b946e76e3 options 2023-05-04 02:12:58 -07:00
MyskYko 920f4dbb7d verbose 2023-05-04 01:49:30 -07:00
MyskYko ec626957b5 option change 2023-05-03 10:46:42 -07:00
MyskYko d1ceefee82 compiler warning 2023-05-02 18:17:46 -07:00
MyskYko 323229a438 fix build 2023-05-02 17:27:01 -07:00
MyskYko ce3843ec8c fix enum 2023-05-02 17:08:02 -07:00
MyskYko 13b0d17169 abc cxx namespace 2023-05-02 17:02:04 -07:00
MyskYko 6e985705fc transduction 2023-05-02 16:48:33 -07:00
Alan Mishchenko eff805a644 Bug fix in choice computation. 2023-04-28 08:02:04 -04:00
Andrey Rogov d785775f64 1. Fix bug (using pDesign without check if == NULL) 
2. Switch type of variables containing file size to (int => long)
 2023-04-28 01:52:01 +03:00
Henner Zeller dfd8fabdd7 Don't #define _DEFAULT_SOURCE if already defined. 2023-04-27 13:44:13 -07:00
Alan Mishchenko cc6834d4cc Unifying random number generation. 2023-04-27 15:40:34 -04:00
Alan Mishchenko 65a756bf01 Command to write the network into an edgelist file, contributed by Cunxi Yu (University of Utah). 2023-04-25 12:58:59 -04:00
Alan Mishchenko 1a91797316 Trying to fix a spurious build error. 2023-04-22 19:17:56 -07:00
Alan Mishchenko 9f4ab5a2c1 Bug fix in SAT sweeping. 2023-04-22 18:37:21 -07:00
Alan Mishchenko b633363f06 Trying to fix a spurious build error. 2023-04-04 10:43:01 +08:00
Alan Mishchenko eaa9da53cd Various unrelated changes. 2023-04-04 10:28:07 +08:00
Alan Mishchenko 36a83acf3c Experiments with sequential mapping. 2023-03-31 19:52:46 +07:00
Alan Mishchenko 08d25f39f2 Various unrelated changes. 2023-03-26 08:15:45 +07:00
Alan Mishchenko 41c01e4fb7 Compiler warning. 2023-03-17 09:59:57 +07:00
Alan Mishchenko 6694add40f Compiler warning. 2023-03-17 09:54:46 +07:00
Alan Mishchenko 1229d1ff07 New options to print out sim info. 2023-03-16 13:03:07 +07:00
Alan Mishchenko a5f4841486 Adding BLIF dumping to MiniAIG. 2023-03-13 20:51:40 +07:00
Alan Mishchenko 6d9c8daece Fix duplicating invs/bufs driving primary outputs in 'write_verilog'. 2023-03-11 22:28:38 +07:00
Alan Mishchenko 8ffb7811c7 New options to print out sim info (warning). 2023-03-11 20:35:23 +07:00
Alan Mishchenko c1b2a64c2e Alternative binary name on Linux. 2023-03-11 20:29:04 +07:00
Alan Mishchenko 7bc6f3396e New options to print out sim info. 2023-03-11 20:25:11 +07:00
Alan Mishchenko 953970e73a Skipping zero partial products. 2023-03-05 11:42:26 +07:00
Alan Mishchenko 9d0e828b85 Fixing compiler error. 2023-03-01 19:12:06 +07:00
Alan Mishchenko 3370370101 Adding switch 'show -d' to keep (not delete) the .dot file after generating the .ps file. 2023-03-01 19:00:44 +07:00
Alan Mishchenko a79dc18eb2 Enabling generation of non-restoring divider. 2023-03-01 18:41:24 +07:00
Alan Mishchenko 8742534db8 More compiler warnings. 2023-03-01 01:12:36 -08:00
alanminko 91aaff2575 More compiler warnings. 2023-02-28 03:07:41 -08:00
Alan Mishchenko 667326b18e Compiler warnings. 2023-02-28 15:53:12 +07:00
Alan Mishchenko 622d142794 Compiler warnings. 2023-02-28 15:40:06 +07:00
Alan Mishchenko b57b546494 Compiler warnings. 2023-02-28 15:16:31 +07:00
Alan Mishchenko 0d0063f7de Experiment with cost functions. 2023-02-28 13:50:35 +07:00
Catherine 2c1c83f75b
Merge pull request #21 from xobs/cast-unsigned-signed 
casts: add casts for unsigned -> signed int
 2023-02-23 01:47:15 +00:00
Catherine f89df8087d Add WASI support in Abc_Clock. 2023-02-23 01:14:48 +00:00
Alan Mishchenko 581c58b9c4 Experiment with choice computation. 2023-02-16 07:14:18 +01:00
Sean Cross 3f9b46591c casts: add casts for unsigned -> signed int 
When compiling on Darwin ARM64 hardware using the Conda clang compiler,
compilation fails due to these casts going from `unsigned` to `int`.

In these cases, a cast appears to be the correct approach. Add a cast
to make the compiler happy.

Signed-off-by: Sean Cross <sean@xobs.io>
 2023-02-15 22:58:24 +08:00
Alan Mishchenko 38ad178e9e Changes and bug fixes in exact synthesis. 2023-02-13 06:39:10 +01:00
Alan Mishchenko bbd0640db2 Enable 'scorr' when AIG has no internal nodes. 2023-02-09 16:15:48 -08:00
Alan Mishchenko 1aecc3373c New command to compute the range of output values. 2023-02-08 15:54:38 -08:00
Alan Mishchenko aa4cada268 Experiments with multiplier generation (linker problem). 2023-02-08 14:49:42 -08:00
Alan Mishchenko 688be5719e Experiments with multiplier generation. 2023-02-08 14:37:38 -08:00
Alan Mishchenko ea0f22de4d Bug fix in &mfs. 2023-02-08 00:25:17 -08:00
Alan Mishchenko 110bac4394 Improvement in truth table printout. 2023-02-08 00:24:43 -08:00
Alan Mishchenko c899a4cb3b Experiments with multipliers. 2023-02-08 00:24:04 -08:00
Alan Mishchenko fa58597321 Updating mfs2 and &mfs to work with larger nodes. 2023-02-05 14:44:44 -08:00
Alan Mishchenko e7ecaee92d Bug fix in supergate generation. 2023-02-05 14:41:18 -08:00
Catherine 18b9c612f4 Add WASI support in Exa4_ManSolve. 2023-02-04 03:14:44 +00:00
Alan Mishchenko 086321a232 Bug fix. 2023-02-02 09:28:51 -08:00
Alan Mishchenko acdb94d1d3 Interfacing SAT sweepers. 2023-02-02 09:15:42 -08:00
Alan Mishchenko 70a07869c6 Updating interface of scorr. 2023-01-28 09:31:13 -10:00