mirror of https://github.com/YosysHQ/abc.git
Adding BLIF dumping to MiniAIG.
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@ -162,6 +162,34 @@ static Mini_Aig_t * Mini_AigStartSupport( int nIns, int nObjsAlloc )
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p->pArray[i] = MINI_AIG_NULL;
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return p;
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}
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static Mini_Aig_t * Mini_AigStartArray( int nIns, int n0InAnds, int * p0InAnds, int nOuts, int * pOuts )
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{
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Mini_Aig_t * p; int i;
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assert( 1+nIns <= n0InAnds );
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p = MINI_AIG_CALLOC( Mini_Aig_t, 1 );
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p->nCap = 2*(n0InAnds + nOuts);
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p->nSize = 2*(n0InAnds + nOuts);
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p->pArray = MINI_AIG_ALLOC( int, p->nCap );
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for ( i = 0; i < 2*(1 + nIns); i++ )
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p->pArray[i] = MINI_AIG_NULL;
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memcpy( p->pArray + 2*(1 + nIns), p0InAnds + 2*(1 + nIns), 2*(n0InAnds - 1 - nIns)*sizeof(int) );
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for ( i = 0; i < nOuts; i++ )
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{
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p->pArray[2*(n0InAnds + i)+0] = pOuts[i];
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p->pArray[2*(n0InAnds + i)+1] = MINI_AIG_NULL;
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}
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return p;
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}
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static Mini_Aig_t * Mini_AigDup( Mini_Aig_t * p )
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{
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Mini_Aig_t * pNew;
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pNew = MINI_AIG_CALLOC( Mini_Aig_t, 1 );
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pNew->nCap = p->nCap;
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pNew->nSize = p->nSize;
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pNew->pArray = MINI_AIG_ALLOC( int, p->nSize );
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memcpy( pNew->pArray, p->pArray, p->nSize * sizeof(int) );
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return pNew;
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}
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static void Mini_AigStop( Mini_Aig_t * p )
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{
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MINI_AIG_FREE( p->pArray );
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@ -352,6 +380,32 @@ static int Mini_AigMuxMulti_rec( Mini_Aig_t * p, int * pCtrl, int * pData, int n
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Res1 = Mini_AigMuxMulti_rec( p, pCtrl+1, pData+nData/2, nData/2 );
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return Mini_AigMux( p, pCtrl[0], Res1, Res0 );
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}
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static Mini_Aig_t * Mini_AigTransformXor( Mini_Aig_t * p )
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{
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Mini_Aig_t * pNew = Mini_AigStart();
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int i, * pCopy = MINI_AIG_ALLOC( int, Mini_AigNodeNum(p) );
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Mini_AigForEachPi( p, i )
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pCopy[i] = Mini_AigCreatePi(pNew);
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Mini_AigForEachAnd( p, i )
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{
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int iLit0 = Mini_AigNodeFanin0(p, i);
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int iLit1 = Mini_AigNodeFanin1(p, i);
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iLit0 = Mini_AigLitNotCond( pCopy[Mini_AigLit2Var(iLit0)], Mini_AigLitIsCompl(iLit0) );
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iLit1 = Mini_AigLitNotCond( pCopy[Mini_AigLit2Var(iLit1)], Mini_AigLitIsCompl(iLit1) );
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if ( iLit0 < iLit1 )
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pCopy[i] = Mini_AigAnd( pNew, iLit0, iLit1 );
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else
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pCopy[i] = Mini_AigXor( pNew, iLit0, iLit1 );
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}
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Mini_AigForEachPo( p, i )
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{
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int iLit0 = Mini_AigNodeFanin0( p, i );
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iLit0 = Mini_AigLitNotCond( pCopy[Mini_AigLit2Var(iLit0)], Mini_AigLitIsCompl(iLit0) );
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pCopy[i] = Mini_AigCreatePo( pNew, iLit0 );
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}
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MINI_AIG_FREE( pCopy );
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return pNew;
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}
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static unsigned s_MiniTruths5[5] = {
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@ -507,6 +561,76 @@ static void Mini_AigDumpVerilog( char * pFileName, char * pModuleName, Mini_Aig_
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fclose( pFile );
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}
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// procedure to dump MiniAIG into a BLIF file
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static void Mini_AigDumpBlif( char * pFileName, char * pModuleName, Mini_Aig_t * p, int fVerbose )
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{
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int i, k, iFaninLit0, iFaninLit1, Length = strlen(pModuleName), nPis = Mini_AigPiNum(p), nPos = Mini_AigPoNum(p);
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char * pObjIsPi = MINI_AIG_FALLOC( char, Mini_AigNodeNum(p) );
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FILE * pFile = fopen( pFileName, "wb" );
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assert( nPis <= 26 );
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if ( pFile == NULL ) { printf( "Cannot open output file %s\n", pFileName ); MINI_AIG_FREE( pObjIsPi ); return; }
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// write interface
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//fprintf( pFile, "// This MiniAIG dump was produced by ABC on %s\n\n", Extra_TimeStamp() );
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fprintf( pFile, ".model %s\n", pModuleName );
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if ( nPis > 0 )
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{
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k = 0;
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fprintf( pFile, ".inputs" );
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Mini_AigForEachPi( p, i )
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{
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pObjIsPi[i] = k;
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fprintf( pFile, " %c", (char)('a'+k++) );
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}
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}
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k = 0;
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fprintf( pFile, "\n.outputs" );
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Mini_AigForEachPo( p, i )
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fprintf( pFile, " o%d", k++ );
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fprintf( pFile, "\n\n" );
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// write LUTs
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Mini_AigForEachAnd( p, i )
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{
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iFaninLit0 = Mini_AigNodeFanin0( p, i );
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iFaninLit1 = Mini_AigNodeFanin1( p, i );
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fprintf( pFile, ".names" );
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if ( pObjIsPi[iFaninLit0 >> 1] >= 0 )
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fprintf( pFile, " %c", (char)('a'+pObjIsPi[iFaninLit0 >> 1]) );
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else
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fprintf( pFile, " n%d", iFaninLit0 >> 1 );
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if ( pObjIsPi[iFaninLit1 >> 1] >= 0 )
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fprintf( pFile, " %c", (char)('a'+pObjIsPi[iFaninLit1 >> 1]) );
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else
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fprintf( pFile, " n%d", iFaninLit1 >> 1 );
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fprintf( pFile, " n%d\n", i );
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if ( iFaninLit0 < iFaninLit1 )
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fprintf( pFile, "%d%d 1\n", !(iFaninLit0 & 1), !(iFaninLit1 & 1) );
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else if ( !(iFaninLit0 & 1) == !(iFaninLit1 & 1) )
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fprintf( pFile, "10 1\n01 1\n" );
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else
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fprintf( pFile, "00 1\n11 1\n" );
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}
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// write assigns
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fprintf( pFile, "\n" );
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k = 0;
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Mini_AigForEachPo( p, i )
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{
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iFaninLit0 = Mini_AigNodeFanin0( p, i );
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fprintf( pFile, ".names" );
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if ( pObjIsPi[iFaninLit0 >> 1] >= 0 )
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fprintf( pFile, " %c", (char)('a'+pObjIsPi[iFaninLit0 >> 1]) );
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else
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fprintf( pFile, " n%d", iFaninLit0 >> 1 );
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fprintf( pFile, " o%d\n", k++ );
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fprintf( pFile, "%d 1\n", !(iFaninLit0 & 1) );
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}
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fprintf( pFile, ".end\n\n" );
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MINI_AIG_FREE( pObjIsPi );
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fclose( pFile );
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if ( fVerbose )
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printf( "Written MiniAIG into the BLIF file \"%s\".\n", pFileName );
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}
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// checks if MiniAIG is normalized (first inputs, then internal nodes, then outputs)
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static int Mini_AigIsNormalized( Mini_Aig_t * p )
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{
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@ -3624,7 +3624,7 @@ Mini_Aig_t * Exa6_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIn
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Abc_PrintTime( 1, "Total runtime", Abc_Clock() - clkTotal );
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return pMini;
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}
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Mini_Aig_t * Mini_AigDup( Mini_Aig_t * p, int ComplIns, int ComplOuts )
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Mini_Aig_t * Mini_AigDupCompl( Mini_Aig_t * p, int ComplIns, int ComplOuts )
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{
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Mini_Aig_t * pNew = Mini_AigStartSupport( Mini_AigPiNum(p), Mini_AigNodeNum(p) );
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Vec_Int_t * vCopies = Vec_IntStartFull( Mini_AigNodeNum(p) ); int k, i = 0, o = 0;
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@ -3713,7 +3713,7 @@ Mini_Aig_t * Exa_ManExactSynthesis6Int( Vec_Wrd_t * vSimsDiv, Vec_Wrd_t * vSimsO
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{
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if ( DivCompl || OutCompl )
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{
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pMini = Mini_AigDup( pTemp = pMini, DivCompl, OutCompl );
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pMini = Mini_AigDupCompl( pTemp = pMini, DivCompl, OutCompl );
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Mini_AigStop( pTemp );
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}
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Mini_AigerWrite( "exa6.aig", pMini, 1 );
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