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1159 Commits

Author SHA1 Message Date
Alan Mishchenko e1b32ee756 Silencing several messages. 2016-06-01 11:57:29 -07:00
Alan Mishchenko 1d26d58a17 Adding switch 'pdr -o' to control using property output in induction. 2016-05-25 13:47:38 -07:00
Alan Mishchenko 7b570b6241 Enabling AIGs without structural hashing (&get -c to import logic network). 2016-05-20 18:01:01 -07:00
Alan Mishchenko 3b62ee4575 Enabling AIGs without structural hashing. 2016-05-20 16:23:48 -07:00
Alan Mishchenko 27c44fd644 Switch &miter -y to convert a two-word miter into a dual-output miter. 2016-05-20 14:03:07 -07:00
Alan Mishchenko 555ed0b158 Enabling AIGs without structural hashing. 2016-05-20 13:50:19 -07:00
Alan Mishchenko 2ded89cca5 Added switch 'bmc3 -r' to disable periodic restarts in the SAT solver. 2016-05-19 22:33:40 -07:00
Alan Mishchenko d7912acfca Bug fix in &demiter. 2016-05-16 17:34:25 -07:00
Alan Mishchenko 8a56721494 Experiments with generating sat assignments. 2016-05-15 16:18:23 -07:00
Alan Mishchenko 4ffbd0b2df Adding switch -r to &dch to prevent combo-loops. 2016-05-13 13:40:08 -07:00
Alan Mishchenko 5b6e5b8178 New command 'expand' to expand SOPs against the offset. 2016-05-12 22:41:20 -07:00
Alan Mishchenko c30819cb05 Cosmetic changes after incorporating new code of 'fxch'. 2016-05-11 19:59:56 -07:00
Bruno Schmitt 3cf495c831 Add a new module which implements the fast extract with cube hashing (fxch) algorithm. 
Removes old partial implementation of this algorithm from the "pla" module.
 2016-05-11 19:41:31 -03:00
Alan Mishchenko 6e8efec57d Experiments with CEC for arithmetic circuits. 2016-05-11 11:07:34 -07:00
Alan Mishchenko 652b279234 Experiments with CEC for arithmetic circuits. 2016-05-08 19:01:46 -07:00
Alan Mishchenko 236d412255 Experiments with CEC for arithmetic circuits. 2016-05-07 19:47:02 -07:00
Alan Mishchenko 40d90ae69c Small changes. 2016-05-04 13:46:07 -07:00
Alan Mishchenko 21896ba6bc Update to &show to show AIGs with XORs and MUXes (derived by &st -m). 2016-05-04 07:22:13 -07:00
Alan Mishchenko 28cbb280b7 Update to &show to show AIGs with XORs and MUXes (derived by &st -m). 2016-05-04 07:05:43 -07:00
Alan Mishchenko a093091004 Fanout restriction in &edge. 2016-04-30 17:47:23 -07:00
Alan Mishchenko 59f3389c9b Experiments with arithmetic circuits. 2016-04-28 20:54:38 -07:00
Alan Mishchenko 53e8647719 Adding option to rehash AIG after mapping. 2016-04-27 18:33:23 -07:00
Alan Mishchenko e8f961671c Extending &satlut to work for 6-LUTs. 2016-04-27 18:12:41 -07:00
Alan Mishchenko e37ec2aac5 Improved algo for edge computation. 2016-04-24 20:49:05 +03:00
Alan Mishchenko f91f23bed0 Adding new switch 'bdd -s' to translate SOP directly into BDD. 2016-04-24 00:13:07 +03:00
Alan Mishchenko 67bfb4ba09 Improved algo for edge computation. 2016-04-23 15:13:22 +03:00
Alan Mishchenko 1b550cb87b Improved algo for edge computation. 2016-04-22 08:36:05 +03:00
Alan Mishchenko 813b0e5851 Experimental algorithm for edge optimization. 2016-04-13 15:54:14 -07:00
Alan Mishchenko 2d6a6f6654 Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG (cubes -x; st). 2016-04-11 21:42:00 -07:00
Alan Mishchenko 2d1d315ece Supporting edge information during mapping. 2016-04-11 18:41:18 -07:00
Alan Mishchenko d0a0cf6395 Command &esop to convert AIG into ESOP. 2016-04-09 17:00:46 -07:00
Alan Mishchenko 3b694a7089 Adding AIG rehashing after LUT mapping in Gia. 2016-04-07 20:03:31 -07:00
Alan Mishchenko 26ec3868f6 Adding AIG rehashing after LUT mapping in Gia. 2016-04-07 19:16:51 -07:00
Alan Mishchenko 887f3c21cc Supporting edges in delay-optimization in &satlut. 2016-04-07 17:15:24 -07:00
Alan Mishchenko f05986f7b3 Supporting edges in delay-optimization in &satlut. 2016-04-07 15:54:50 -07:00
Alan Mishchenko 95ab749087 Supporting edges in delay-optimization in &satlut. 2016-04-07 13:20:41 -07:00
Alan Mishchenko b31b6fec77 Supporting edge information during mapping. 2016-04-06 15:43:03 -07:00
Alan Mishchenko ac7a799076 Improvements to delay-optimization in &satlut. 2016-04-04 14:27:14 -07:00
Alan Mishchenko 720082753f Improvements to delay-optimization in &satlut. 2016-04-04 12:51:05 -07:00
Alan Mishchenko 4a954c1b23 Improvements to delay-optimization in &satlut. 2016-04-04 08:43:22 -07:00
Alan Mishchenko e0ad9de7ea Improvements to delay-optimization in &satlut. 2016-04-03 16:44:13 -07:00
Alan Mishchenko d53161a7e1 Enabling native Gia visualization in &show. 2016-04-03 15:42:08 -07:00
Alan Mishchenko 7724dfcca2 Windowing for technology mapping. 2016-03-30 21:51:50 -07:00
Alan Mishchenko 847d661bee Change error to warning in 'scorr'. 2016-03-09 09:33:10 +09:00
Alan Mishchenko cf702af6f1 New hierarchical TT NPN matching. 2016-02-26 18:20:57 +08:00
Alan Mishchenko 390a145f0a Adding support for a different bit-blasting of a multiplier and squarer. 2016-02-13 15:15:01 -08:00
Alan Mishchenko 66796c3808 Experiments with SAT-based mapping. 2016-02-08 16:29:36 -08:00
Alan Mishchenko f5ee46eb3c New command to dump LUT network. 2016-01-16 17:35:46 -08:00
Alan Mishchenko c4446189a9 Changes to PDR to compute f-inf clauses and import invariant (or clauses) as a network. 2016-01-14 20:42:22 -08:00
Alan Mishchenko 87f6828d50 Adding support for delay/area tradeoff. 2016-01-13 12:13:54 -08:00