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2,758 Commits 27 Branches 57 Tags 58 MiB
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2758 Commits

Author SHA1 Message Date
Alan Mishchenko e033a62282 Code restructuring. 2014-09-16 12:13:25 -07:00
Alan Mishchenko 1d5cb52e4a Improvements to Boolean matching. 2014-09-16 11:56:40 -07:00
Alan Mishchenko 61e58b2d56 Compiler error (duplicate typedef). 2014-09-15 08:54:07 -07:00
Alan Mishchenko 501c3f0b1e Compiler warnings. 2014-09-12 13:53:04 -07:00
Alan Mishchenko 39c68e72e4 Replacing tabs with spaces. 2014-09-12 13:46:11 -07:00
Alan Mishchenko dcb7d0d3fc New word-level representation package. 2014-09-12 13:40:48 -07:00
Alan Mishchenko ae7e286213 Resetting the random seed in 'sparsify'. 2014-09-11 18:50:15 -07:00
Alan Mishchenko 7171812ff1 Updating timing info during normalization. 2014-09-10 15:28:46 -07:00
Alan Mishchenko c7daa8cafd Updating timing info during normalization. 2014-09-10 15:28:03 -07:00
Alan Mishchenko 49f2ec22b9 Bug fix in transferring timing info. 2014-09-09 22:50:15 -07:00
Alan Mishchenko a5e93ff075 Corner-case bug fix in balancing. 2014-09-08 09:33:11 -07:00
Alan Mishchenko 233e12610a Added command 'move_names'. 2014-08-28 13:06:02 -07:00
Alan Mishchenko 79c1928cf9 Added command 'move_names'. 2014-08-28 13:04:47 -07:00
Alan Mishchenko 3c51dd47b5 Tuning LUT mapping flow. 2014-08-28 00:11:24 -07:00
Alan Mishchenko 70a236379b Tuning LUT mapping flow. 2014-08-27 23:17:33 -07:00
Alan Mishchenko 17343bf144 Compiler warning. 2014-08-27 23:03:39 -07:00
Alan Mishchenko ce74153c9f Tuning LUT mapping flow. 2014-08-27 22:59:21 -07:00
Alan Mishchenko 6db6607114 Improvements BLIF parser. 2014-08-27 18:47:45 -07:00
Alan Mishchenko 9c154cfe61 Improvements to DSD balancing. 2014-08-27 12:23:31 -07:00
Alan Mishchenko 66d9a80b3d Adding commands to save/load best network. 2014-08-26 21:28:26 -07:00
Alan Mishchenko 70a3474849 Improvements to the timing manager. 2014-08-25 20:47:11 -05:00
Alan Mishchenko 5c30eb10ef Improving GIA interfaces for some procedures. 2014-08-25 17:33:53 -07:00
Alan Mishchenko 47dde4e478 Correcting incorrect handling of timing in several &-commands. 2014-08-25 16:55:39 -07:00
Alan Mishchenko cbbf78e6f4 Improving print-out of 'dsd -p'. 2014-08-22 22:18:38 -07:00
Alan Mishchenko c344f3e38c Propagating timing support to the new synthesis/mapping commands. 2014-08-20 22:12:51 -07:00
Alan Mishchenko 6dbaa4d0f8 Extended command &cone to extract timing critical cones. 2014-08-19 23:30:17 -07:00
Alan Mishchenko 3ef00645b8 Added command 'sparsify' to derive ISF from CSF. 2014-08-18 22:42:48 -07:00
Alan Mishchenko 65f9b73505 Changing default CNF generation in &bmc. 2014-08-18 20:19:32 -07:00
Alan Mishchenko 7c8136c82d Added DSD-based collapsing &dsd. 2014-08-16 18:38:34 -07:00
Alan Mishchenko 1537244935 Added DSD-based collapsing &dsd. 2014-08-16 18:36:41 -07:00
Alan Mishchenko ec5bc5825d Adding specialized matching to 'if'. 2014-08-16 18:34:20 -07:00
Alan Mishchenko 18ed4d3448 Added DSD-based collapsing &dsd. 2014-08-16 18:31:46 -07:00
Alan Mishchenko 97e620a4b7 Adding specialized matching to 'if'. 2014-08-16 18:28:41 -07:00
Alan Mishchenko 06100279cd Added DSD-based collapsing &dsd. 2014-08-16 11:54:49 -07:00
Alan Mishchenko c8bfe83e55 Suggested fix to allow .constr files to have empty lines. 2014-08-13 16:46:20 -07:00
Alan Mishchenko f907347484 Enabling circuit solver in &fraig. 2014-08-12 18:54:43 -07:00
Alan Mishchenko 9055265394 Bug fix in &fraig -L <num>. 2014-08-12 16:23:52 -07:00
Alan Mishchenko 99a917caf3 Bug fix in &fraig -L <num>. 2014-08-12 16:20:03 -07:00
Alan Mishchenko 0722dde6f9 Increasing the size of pre-allocated memory in &syn2. 2014-08-11 18:34:14 -07:00
Alan Mishchenko 68ce0bc1c1 Adding delay optimization to synthesis script &syn2. 2014-08-08 12:45:28 -07:00
Alan Mishchenko 35b816dd57 Enabling cofactoring in the mapper. 2014-08-06 14:18:20 -07:00
Alan Mishchenko ae64dc0796 Profiling code for SOP/DSD/LMS balancing. 2014-08-04 21:36:01 -07:00
Alan Mishchenko a3a6002b3d Compiler warnings. 2014-08-04 15:34:34 -07:00
Alan Mishchenko 1d9d6814ee Enabling ISOP-based minimization in 'collapse' if EXDC is available. 2014-08-04 10:53:08 -07:00
Alan Mishchenko 82aec90c6c Compiler warnings. 2014-08-02 17:06:08 -07:00
Alan Mishchenko edba505d9d Profiling code for SOP/DSD/LMS balancing. 2014-08-02 17:01:48 -07:00
Alan Mishchenko 62bc45d1fb Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, such as [7:7], which seems to help in some cases. 2014-08-02 17:00:24 -07:00
Alan Mishchenko 7fb1954268 Small changes. 2014-07-29 22:49:10 -07:00
Alan Mishchenko 6a69a9139c Adding support for standard-cell mapping. 2014-07-28 11:31:31 -07:00
Alan Mishchenko 674dcf2a6e Generating abstraction of standard cell library. 2014-07-26 16:49:32 -07:00