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313 Commits

Author SHA1 Message Date
Alan Mishchenko a718318740 Various changes. 2021-09-02 22:54:19 -07:00
Alan Mishchenko 85a94766a6 Compiler warnings. 2021-08-23 19:56:26 -07:00
Alan Mishchenko e8ac47641f Suggested changes to collect and pass timing information. 2021-08-12 18:25:00 -07:00
Alan Mishchenko 0ce11851bc Updating LUT synthesis code. 2021-05-16 20:33:53 -07:00
Alan Mishchenko e6a47c3e41 Disable cube-sort when deriving SOPs. 2021-05-11 15:54:43 -07:00
Alan Mishchenko aa9fe1f240 Updating LUT synthesis code. 2021-05-11 15:04:15 -07:00
Alan Mishchenko 645752f7d6 Making sure read_bench can read nodes up to 15 inputs. 2021-04-30 16:12:15 -07:00
Alan Mishchenko de71e5f610 Passing node labels. 2021-04-26 18:52:44 -07:00
Alan Mishchenko ce95366e51 Trying to explicitly compute don't-cares during optimization. 2020-11-01 14:23:17 -08:00
Alan Mishchenko 2325cd77e3 Adding an option to write Verilog with LUT instances (compiler warnings). 2020-10-31 16:14:52 -07:00
Alan Mishchenko f9af41ba1b Adding an option to write Verilog with LUT instances. 2020-10-31 15:08:40 -07:00
Alan Mishchenko b2aa245eaa Fixing a clang error related to 'unlink'. 2020-10-09 23:28:23 -07:00
Alan Mishchenko ada073110e New command 'read_sf'. 2020-10-01 21:24:32 -07:00
Alan Mishchenko c9bebe157b Ongoing changes to the simulator. 2020-03-09 13:16:22 +02:00
Alan Mishchenko 19b8d9bf7c Adding CNF variable mapping rules. 2020-01-18 16:42:02 -08:00
Alan Mishchenko d1462693cf Updates to JSON parser. 2019-12-02 22:53:26 -08:00
Alan Mishchenko 235176d8fb Updates to JSON parser. 2019-12-02 15:43:12 -08:00
Alan Mishchenko 787e3e1d12 Adding logfile dump to print_status. 2019-11-25 17:54:18 +07:00
Alan Mishchenko 3699f8beb9 Dumping multiple counter-examples. 2019-11-19 21:13:07 +08:00
Alan Mishchenko 4242cec36e Dumping multiple counter-examples. 2019-11-19 21:08:02 +08:00
Alan Mishchenko 2eebfc2eb5 Dumping multiple counter-examples. 2019-11-19 21:02:27 +08:00
Alan Mishchenko 0d24b4e4ca Bug fix in parsing hierarchical BLIF with mapping. 2019-11-18 22:29:09 +08:00
Alan Mishchenko 379b6a2b77 Fix read_bench to read standard gate names in lower-case. 2019-08-28 00:52:46 +09:00
Alan Mishchenko 7e8fc63d90 Adding synonym of 'read_dsd'. 2019-06-20 12:23:08 +02:00
Alan Mishchenko 7ccb25bfe9 Modifying 'write_truth' to dump truth table in hex. 2019-05-07 07:27:31 +08:00
Alan Mishchenko f5320744fa Adding switch 'read_truth -f <file_name>' to read truth table from file. 2019-04-15 20:20:26 -07:00
Alan Mishchenko 01569b8f5f Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc. 2019-03-05 15:57:50 -08:00
Alan Mishchenko bc288a7633 Suggested white-space changes for fewer gcc warnings. 2019-03-04 14:29:57 -08:00
Alan Mishchenko 881b5a24a0 Add skip feature to CEX printing. 2019-02-08 13:06:20 -08:00
Alan Mishchenko b3d81b5f76 Exploring other ways of CEX writing. 2019-01-21 14:57:05 -08:00
Alan Mishchenko d4ce4cc982 Undoing some recent changes for improved CEX writing. 2019-01-21 11:49:35 -08:00
Alan Mishchenko 81b263e35a Fixing the problem with outputting word-level CEXes after retiming. 2019-01-18 12:34:59 -08:00
Alan Mishchenko 4d8c72d0e9 Fixing the problem with outputting word-level CEXes after retiming. 2019-01-17 11:07:31 -08:00
Alan Mishchenko d05f89d997 Fixing the problem with outputting word-level CEXes. 2019-01-16 17:57:40 -08:00
Alan Mishchenko 12908d3c25 Various usability changes. 2018-11-18 21:01:30 -08:00
Alan Mishchenko a8faa2b55c Adding switch to 'write_pla' to write random onset minterms of the first PO function (bug fix). 2018-09-29 08:26:48 -07:00
Alan Mishchenko 75ed8581dd Adding switch to 'write_pla' to write random onset minterms of the first PO function. 2018-09-28 17:46:06 -07:00
Alan Mishchenko b729c737b5 Adding switch 'clp -o' to reverse initial variable ordering. 2018-06-07 15:53:12 -07:00
Alan Mishchenko a2d59be3f7 Integrating SAT-based CEX minimization (bug fix). 2018-03-25 18:19:06 -07:00
Alan Mishchenko e639e8fd1b Integrating SAT-based CEX minimization. 2018-03-25 16:46:09 -07:00
Alan Mishchenko 680af1891b Bug fix in 'write_aiger_cex'. 2017-12-20 15:41:39 -08:00
Alan Mishchenko 1743979b75 Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes. 2017-12-03 14:39:11 -08:00
Alan Mishchenko d0286dce37 Fixing minimize_assuptions using Glucose. 2017-10-02 21:31:34 +03:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 2e56f44c66 Compiler warnings. 2017-07-22 11:41:17 +07:00
Alan Mishchenko 8bff9aa1cd Adding PDR with abstraction. 2017-02-10 17:36:20 -08:00
Alan Mishchenko f2d096c9f0 Improving CEX minimization. 2017-02-10 13:20:20 -08:00
Alan Mishchenko f34029dd09 Improvements in AIG visualization. 2017-02-05 12:28:34 -08:00
Alan Mishchenko e21c7d72f3 Updates to arithmetic verification. 2017-01-30 08:39:26 -08:00
Alan Mishchenko b3514ee7e0 Commenting out bailout in 'print_cex' when CEX has latches initialized to 1. 2016-11-30 12:07:08 -08:00