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5854 Commits

Author SHA1 Message Date
Alan Mishchenko ca2a410095 Add log dump to %ufar. 2026-04-04 09:04:24 -07:00
Alan Mishchenko cd2998b5c7 Adding name-based input reordering in &cec. 2026-04-03 21:18:41 -07:00
Alan Mishchenko bef23270f8 Improvements to command "history". 2026-03-27 20:09:54 -07:00
Alan Mishchenko b8059c310a Add support for second Verilog files in %ysoys and &cec 2026-03-27 19:24:31 -07:00
Alan Mishchenko 6aaf0db1e1 Fixing the required time problem. 2026-03-25 10:03:26 -07:00
Alan Mishchenko 60e0303e3a Fix a mismatch in cut selection. 2026-03-24 20:16:09 -07:00
Alan Mishchenko 3881f2de37 Updated to &sprove. 2026-03-23 17:34:59 -07:00
Alan Mishchenko ceebb2d167 Updated to &sprove. 2026-03-23 14:55:27 -07:00
Alan Mishchenko 24917213df Updates to &if mapper. 2026-03-19 20:18:08 -07:00
Alan Mishchenko ca0fc3ed29 Adding support for Verilog dumping in "lutexact'. 2026-03-19 18:37:32 -07:00
Alan Mishchenko cf5aef3889 Fix compiler problems. 2026-03-10 22:26:43 -07:00
Alan Mishchenko fa5029da95 Updates to &if mapper. 2026-03-10 22:19:37 -07:00
Alan Mishchenko 7ae0f4966a Adding gla to sprove. 2026-03-08 12:04:38 -07:00
Alan Mishchenko a745d5ec81 Adding profiling to %ufar. 2026-03-08 10:27:12 -07:00
Alan Mishchenko ba69519d73 Adding command for calling external solvers. 2026-03-08 10:26:27 -07:00
Alan Mishchenko c92cfab80b Adding new line at the end of AIGER files. 2026-03-08 10:25:15 -07:00
alanminko 7553ef9760
Merge pull request #471 from phyzhenli/master 
Fix &synch2 crash with creating wrong mapping
 2026-03-07 06:54:56 -08:00
Drew Lewis ee40e40d09 Have the buffer grow with a 2x factor to avoid O(n^2) work when reading big files. 
Signed-off-by: Drew Lewis <cannada@google.com>
 2026-03-02 22:22:27 +00:00
Alan Mishchenko f3a17d343a Fixing assertion failure introduced by a recent PR. 2026-02-26 20:08:03 -08:00
Alan Mishchenko 4e5c5e62af Compiler problem. 2026-02-25 20:18:28 -08:00
Alan Mishchenko c1937d12ac Improvements to &sprove. 2026-02-25 20:00:57 -08:00
Alan Mishchenko d5c1f2cfe1 Adding callbacks to "scorr" and "&scorr". 2026-02-25 20:00:28 -08:00
Alan Mishchenko ef54c1daea Updating interface of &cec. 2026-02-24 14:59:13 -08:00
Jonathan Greene 3b5036a1e1 Fix required time handling for unconstrained POs, infinity arithmetic, and absDup cosmetic 
- Tim_ManInitPoRequiredAll: only overwrite PO required times when ALL are
  unconstrained; preserve user-specified constraints
- Gia_ObjPropagateRequired: propagate infinity unchanged through LUTs
- Tim_ManGetCoRequired: guard against infinity minus delay arithmetic
- Gia_ManDelayTraceLut: handle infinite required times in slack computation;
  allow negative slack to report timing violations
- Tim_ManCreate: fix required-time loading to address actual POs via
  Tim_ManForEachPo instead of p->pCos[] (wrong for designs with boxes)
- Tim_ManGetArrTimes/Tim_ManGetReqTimes: fix loop-exit detection using
  boolean flag instead of comparing iterator index against PO/PI count
- Gia_ManPrintFlopClasses: use Gia_ManRegBoxNum instead of Gia_ManRegNum

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-21 16:54:27 -08:00
Jonathan Greene 771e70381c Fix two bugs causing problems with &trace and boxes. 2026-02-20 11:51:16 -08:00
Jonathan Greene 71c24a4812 Fix backward required-time propagation through boxes 2026-02-19 13:24:41 -08:00
Alan Mishchenko c7ea67b7df Update command "history". 2026-02-18 12:19:32 -08:00
Alan Mishchenko 6c8b2cfa3b Compiler problem. 2026-02-18 12:19:04 -08:00
Alan Mishchenko 3dd086febe New command &divide, etc. 2026-02-18 10:02:42 -08:00
Alan Mishchenko 3cdb1c4c3b Dumping LUT-mapped networks in Vivado-readable Verilog. 2026-02-15 19:26:35 -08:00
Alan Mishchenko 8475386dfa Making %ufar preserve AIG name. 2026-02-13 09:52:37 -08:00
Alan Mishchenko 2726f0e470 Fixing compiler problem. 2026-02-13 07:12:50 -08:00
Alan Mishchenko 3285adaf32 Updating &sprove to run %ufar. 2026-02-13 07:04:50 -08:00
Alan Mishchenko 90be4816ce Updating delay trace for LUT mapping. 2026-02-08 22:50:12 -08:00
Alan Mishchenko 6339de7296 Fix box flop issue. 2026-02-05 23:16:02 -08:00
Alan Mishchenko b60994e143 Bug fix. 2026-02-03 21:32:52 -08:00
Alan Mishchenko 8573cb98f6 Bug fix in %blast. 2026-02-03 11:52:21 -08:00
Alan Mishchenko ccafa23e40 Extending &funtrace. 2026-02-03 11:17:26 -08:00
Alan Mishchenko b50fd7a10a Adding support for not merging some flops after &scorr. 2026-02-02 17:12:15 -08:00
Alan Mishchenko 367b407fba Extending "lutexact" to get function from the current network. 2026-02-01 19:47:14 -08:00
Alan Mishchenko 5899aa5df1 Allow for backward compatibility (when nly PI/PO timing is given). 2026-02-01 19:24:35 -08:00
alanminko 70a12750c1
Merge pull request #475 from wjrforcyber/master 
Fix(&put): Missing spec in cec
 2026-02-01 07:55:20 -08:00
alanminko 5fd7c57407
Merge pull request #477 from YosysHQ/wasi_upstream 
MINGW and WASI compile fixes (from YosysHQ fork)
 2026-02-01 07:55:05 -08:00
Alan Mishchenko b6105230bf Transforming init1 states. 2026-01-30 17:29:15 +07:00
Miodrag Milanovic f2ae808236 MINGW proper pthread handling 2026-01-29 09:28:21 +01:00
Alan Mishchenko ade1882ffc Commenting out an assertion. 2026-01-29 11:33:37 +07:00
Alan Mishchenko 29656286cf New command &init1. 2026-01-28 18:39:21 +07:00
Miodrag Milanovic 6fcdfdbc5e WASI compile fixes 2026-01-28 09:52:01 +01:00
Alan Mishchenko 71e163571a Rename ID mapping switch in &verify. 2026-01-27 22:03:41 +07:00
Alan Mishchenko dd21791031 Extending &verify to handle combinational designs. 2026-01-27 21:52:26 +07:00