mirror of https://github.com/YosysHQ/abc.git
Extending &verify to handle combinational designs.
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@ -5816,10 +5816,12 @@ void Gia_ManProdAdderGen( int nArgA, int nArgB, int Seed, int fSigned, int fCla
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/**Function*************************************************************
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Synopsis []
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Synopsis [Adds a dummy flop to the design.]
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Description [Duplicates the AIG while adding one flop with constant 0 input
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and no fanout. Handles designs with boxes by also duplicating
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the timing manager with an additional CI/CO pair.]
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Description []
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SideEffects []
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SeeAlso []
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@ -5827,11 +5829,13 @@ void Gia_ManProdAdderGen( int nArgA, int nArgB, int Seed, int fSigned, int fCla
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***********************************************************************/
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Gia_Man_t * Gia_ManDupAddFlop( Gia_Man_t * p )
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{
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extern Tim_Man_t * Tim_ManDupAddFlop( Tim_Man_t * p, int fUnitDelay );
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Gia_Man_t * pNew;
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Gia_Obj_t * pObj;
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int i;
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pNew = Gia_ManStart( Gia_ManObjNum(p) + 2 );
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pNew->pName = Abc_UtilStrsav(p->pName);
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pNew->pSpec = Abc_UtilStrsav(p->pSpec);
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Gia_ManConst0(p)->Value = 0;
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Gia_ManForEachCi( p, pObj, i )
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pObj->Value = Gia_ManAppendCi( pNew );
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@ -5840,8 +5844,40 @@ Gia_Man_t * Gia_ManDupAddFlop( Gia_Man_t * p )
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pObj->Value = Gia_ManAppendAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
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Gia_ManForEachCo( p, pObj, i )
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Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
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Gia_ManAppendCo( pNew, 0 );
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Gia_ManAppendCo( pNew, 0 );
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Gia_ManSetRegNum( pNew, Gia_ManRegNum(p)+1 );
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if ( p->pManTime )
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pNew->pManTime = Tim_ManDupAddFlop( (Tim_Man_t *)p->pManTime, 0 );
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if ( p->pAigExtra )
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pNew->pAigExtra = Gia_ManDup( p->pAigExtra );
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if ( p->vCiArrs )
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{
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pNew->vCiArrs = Vec_IntDup( p->vCiArrs );
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Vec_IntPush( pNew->vCiArrs, 0.0 ); // default arrival for new flop output
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}
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if ( p->vCoReqs )
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{
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pNew->vCoReqs = Vec_IntDup( p->vCoReqs );
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Vec_IntPush( pNew->vCoReqs, ABC_INFINITY ); // default required for new flop input
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}
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if ( p->vCoArrs )
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{
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pNew->vCoArrs = Vec_IntDup( p->vCoArrs );
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Vec_IntPush( pNew->vCoArrs, 0.0 ); // default arrival for new flop input
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}
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if ( p->vCoAttrs )
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{
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pNew->vCoAttrs = Vec_IntDup( p->vCoAttrs );
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Vec_IntPush( pNew->vCoAttrs, 0 ); // default attribute for new flop input
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}
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// copy other timing-related fields
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pNew->And2Delay = p->And2Delay;
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if ( p->vInArrs )
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pNew->vInArrs = Vec_FltDup( p->vInArrs );
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if ( p->vOutReqs )
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pNew->vOutReqs = Vec_FltDup( p->vOutReqs );
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pNew->DefInArrs = p->DefInArrs;
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pNew->DefOutReqs = p->DefOutReqs;
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return pNew;
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}
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@ -1128,6 +1128,16 @@ int Gia_ManVerifyWithBoxes( Gia_Man_t * pGia, int nBTLimit, int nTimeLim, int fS
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// compute the miter
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if ( fSeq )
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{
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extern Gia_Man_t * Gia_ManDupAddFlop( Gia_Man_t * p );
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if ( Gia_ManRegNum(pGia0) == 0 ) {
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pGia0 = Gia_ManDupAddFlop( pMiter = pGia0 );
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Gia_ManStop( pMiter );
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}
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if ( Gia_ManRegNum(pGia1) == 0 ) {
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pGia1 = Gia_ManDupAddFlop( pMiter = pGia1 );
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Gia_ManStop( pMiter );
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}
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pMiter = Gia_ManMiter( pGia0, pGia1, 0, 0, 1, 0, fVerbose );
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if ( pMiter )
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{
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@ -152,6 +152,103 @@ Tim_Man_t * Tim_ManDup( Tim_Man_t * p, int fUnitDelay )
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return pNew;
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}
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/**Function*************************************************************
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Synopsis [Duplicates the timing manager while adding one flop.]
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Description [Creates a new timing manager with one additional CI/CO pair
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for a new flop. The new CI and CO are added at the end,
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after all box inputs/outputs.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Tim_Man_t * Tim_ManDupAddFlop( Tim_Man_t * p, int fUnitDelay )
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{
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Tim_Man_t * pNew;
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Tim_Box_t * pBox;
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Tim_Obj_t * pObj;
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float * pDelayTable, * pDelayTableNew;
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int i, k, nInputs, nOutputs;
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// clear traversal IDs
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Tim_ManForEachCi( p, pObj, i )
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pObj->TravId = 0;
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Tim_ManForEachCo( p, pObj, i )
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pObj->TravId = 0;
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// create new manager with one additional CI and CO
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pNew = Tim_ManStart( p->nCis + 1, p->nCos + 1 );
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// copy existing CI connectivity information
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memcpy( pNew->pCis, p->pCis, sizeof(Tim_Obj_t) * p->nCis );
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// Initialize the new CI (flop output)
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pNew->pCis[p->nCis].Id = p->nCis;
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pNew->pCis[p->nCis].iObj2Box = -1;
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pNew->pCis[p->nCis].iObj2Num = -1;
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pNew->pCis[p->nCis].timeArr = 0.0;
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pNew->pCis[p->nCis].timeReq = TIM_ETERNITY;
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// copy existing CO connectivity information
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memcpy( pNew->pCos, p->pCos, sizeof(Tim_Obj_t) * p->nCos );
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// Initialize the new CO (flop input)
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pNew->pCos[p->nCos].Id = p->nCos;
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pNew->pCos[p->nCos].iObj2Box = -1;
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pNew->pCos[p->nCos].iObj2Num = -1;
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pNew->pCos[p->nCos].timeArr = 0.0;
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pNew->pCos[p->nCos].timeReq = TIM_ETERNITY;
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if ( fUnitDelay )
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{
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// clear PI arrival and PO required
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Tim_ManInitPiArrivalAll( pNew, 0.0 );
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Tim_ManInitPoRequiredAll( pNew, (float)TIM_ETERNITY );
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}
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// duplicate delay tables
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if ( Tim_ManDelayTableNum(p) > 0 )
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{
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pNew->vDelayTables = Vec_PtrStart( Vec_PtrSize(p->vDelayTables) );
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Tim_ManForEachTable( p, pDelayTable, i )
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{
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if ( pDelayTable == NULL )
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continue;
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assert( i == (int)pDelayTable[0] );
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nInputs = (int)pDelayTable[1];
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nOutputs = (int)pDelayTable[2];
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pDelayTableNew = ABC_ALLOC( float, 3 + nInputs * nOutputs );
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pDelayTableNew[0] = (int)pDelayTable[0];
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pDelayTableNew[1] = (int)pDelayTable[1];
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pDelayTableNew[2] = (int)pDelayTable[2];
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for ( k = 0; k < nInputs * nOutputs; k++ )
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if ( pDelayTable[3+k] == -ABC_INFINITY )
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pDelayTableNew[3+k] = -ABC_INFINITY;
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else
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pDelayTableNew[3+k] = fUnitDelay ? (float)fUnitDelay : pDelayTable[3+k];
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assert( Vec_PtrEntry(pNew->vDelayTables, i) == NULL );
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Vec_PtrWriteEntry( pNew->vDelayTables, i, pDelayTableNew );
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}
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}
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// duplicate boxes
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if ( Tim_ManBoxNum(p) > 0 )
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{
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pNew->vBoxes = Vec_PtrAlloc( Tim_ManBoxNum(p) );
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Tim_ManForEachBox( p, pBox, i )
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{
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Tim_ManCreateBox( pNew, pBox->Inouts[0], pBox->nInputs,
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pBox->Inouts[pBox->nInputs], pBox->nOutputs, pBox->iDelayTable, pBox->fBlack );
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Tim_ManBoxSetCopy( pNew, i, pBox->iCopy );
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}
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}
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return pNew;
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}
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/**Function*************************************************************
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Synopsis [Trims the timing manager.]
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