mirror of https://github.com/YosysHQ/abc.git
Dumping LUT-mapped networks in Vivado-readable Verilog.
This commit is contained in:
Alan Mishchenko
parent
8475386dfa
commit
3cdb1c4c3b
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@ -1292,12 +1292,201 @@ static void GiaHie_DumpInterfaceAssigns( Gia_Man_t * p, char * pFileName )
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fclose( pFile );
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}
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/**Function*************************************************************
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Synopsis [Dumps mapped AIG as LUT6 instances in Verilog]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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static void GiaHie_DumpMappedLuts( Gia_Man_t * p, char * pFileName )
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{
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int i, k, iFanin, nLutSize, nDigits;
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FILE * pFile;
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Vec_Int_t * vLeaves;
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word * pTruth;
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Gia_Obj_t * pObj;
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// Check if AIG is mapped
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if ( !Gia_ManHasMapping(p) )
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{
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printf( "Cannot write LUT-based Verilog because AIG is not mapped.\n" );
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return;
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}
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pFile = fopen( pFileName, "wb" );
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if ( pFile == NULL )
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{
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printf( "Cannot open output file \"%s\".\n", pFileName );
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return;
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}
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nDigits = Abc_Base10Log( Gia_ManObjNum(p) );
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if ( nDigits < 3 )
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nDigits = 3;
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// Write header
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fprintf( pFile, "`timescale 1ns/1ps\n\n" );
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// Write LUT module definitions for Yosys compatibility (compact version)
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fprintf( pFile, "module LUT2 #( parameter INIT = 04\'h0 ) ( output O, input I0, I1 );\n" );
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fprintf( pFile, " assign O = INIT[ {I1, I0} ];\n" );
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fprintf( pFile, "endmodule\n" );
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fprintf( pFile, "module LUT3 #( parameter INIT = 08\'h0 ) ( output O, input I0, I1, I2 );\n" );
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fprintf( pFile, " assign O = INIT[ {I2, I1, I0} ];\n" );
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fprintf( pFile, "endmodule\n" );
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fprintf( pFile, "module LUT4 #( parameter INIT = 16\'h0 ) ( output O, input I0, I1, I2, I3 );\n" );
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fprintf( pFile, " assign O = INIT[ {I3, I2, I1, I0} ];\n" );
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fprintf( pFile, "endmodule\n" );
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fprintf( pFile, "module LUT5 #( parameter INIT = 32\'h0 ) ( output O, input I0, I1, I2, I3, I4 );\n" );
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fprintf( pFile, " assign O = INIT[ {I4, I3, I2, I1, I0} ];\n" );
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fprintf( pFile, "endmodule\n" );
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fprintf( pFile, "module LUT6 #( parameter INIT = 64\'h0 ) ( output O, input I0, I1, I2, I3, I4, I5 );\n" );
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fprintf( pFile, " assign O = INIT[ {I5, I4, I3, I2, I1, I0} ];\n" );
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fprintf( pFile, "endmodule\n\n" );
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// Write main module
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fprintf( pFile, "module " );
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GiaHie_DumpModuleName( pFile, p->pName );
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fprintf( pFile, " (\n" );
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GiaHie_DumpPortDecls( p, pFile );
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fprintf( pFile, "\n);\n\n" );
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// Declare wires for inputs (using object IDs like regular &write_ver)
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if ( Gia_ManCiNum(p) )
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{
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fprintf( pFile, " wire " );
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GiaHie_WriteObjRange( pFile, p, 0, Gia_ManCiNum(p), nDigits, 7, 4, 0, 1 );
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fprintf( pFile, ";\n\n" );
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GiaHie_DumpInputAssigns( p, pFile, nDigits );
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fprintf( pFile, "\n" );
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}
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// Declare wires for outputs (using object IDs like regular &write_ver)
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if ( Gia_ManCoNum(p) )
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{
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fprintf( pFile, " wire " );
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GiaHie_WriteObjRange( pFile, p, 0, Gia_ManCoNum(p), nDigits, 7, 4, 0, 0 );
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fprintf( pFile, ";\n\n" );
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GiaHie_DumpOutputAssigns( p, pFile, nDigits );
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fprintf( pFile, "\n" );
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}
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// Declare internal wires for LUT outputs (10 per line)
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{
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int nWiresPerLine = 10;
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int nWireCount = 0;
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int fFirst = 1;
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Gia_ManForEachLut( p, i )
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{
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if ( nWireCount == 0 )
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fprintf( pFile, " wire " );
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if ( !fFirst )
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fprintf( pFile, ", " );
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fprintf( pFile, "n%0*d", nDigits, i );
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fFirst = 0;
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nWireCount++;
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if ( nWireCount == nWiresPerLine )
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{
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fprintf( pFile, ";\n" );
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nWireCount = 0;
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fFirst = 1;
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}
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}
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if ( nWireCount > 0 )
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fprintf( pFile, ";\n" );
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}
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fprintf( pFile, "\n" );
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// Initialize truth table computation
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vLeaves = Vec_IntAlloc( 6 );
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Gia_ObjComputeTruthTableStart( p, 6 );
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// Write LUT6 instances
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Gia_ManForEachLut( p, i )
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{
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nLutSize = Gia_ObjLutSize( p, i );
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// Collect LUT inputs
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Vec_IntClear( vLeaves );
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Gia_LutForEachFanin( p, i, iFanin, k )
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Vec_IntPush( vLeaves, iFanin );
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// Compute truth table
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pTruth = Gia_ObjComputeTruthTableCut( p, Gia_ManObj(p, i), vLeaves );
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// Write LUT instance - use appropriate size LUT based on inputs
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if ( nLutSize <= 1 )
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nLutSize = 2; // minimum LUT size is 2
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// Determine INIT width and padding
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int nInitBits = (1 << nLutSize);
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unsigned long long truthValue = (nLutSize <= 6) ? pTruth[0] : 0;
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// Mask truth value to the appropriate number of bits
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if ( nLutSize < 6 )
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truthValue &= ((1ULL << nInitBits) - 1);
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// Write LUT instance with padding for alignment
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fprintf( pFile, " (* DONT_TOUCH = \"yes\" *) LUT%d #(", nLutSize );
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// Write INIT parameter with appropriate width and padding aligned to 64-bit width
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if ( nLutSize == 2 )
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fprintf( pFile, ".INIT(04'h%01llx )) u_lut%0*d (", truthValue, nDigits, i );
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else if ( nLutSize == 3 )
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fprintf( pFile, ".INIT(08'h%02llx )) u_lut%0*d (", truthValue, nDigits, i );
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else if ( nLutSize == 4 )
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fprintf( pFile, ".INIT(16'h%04llx )) u_lut%0*d (", truthValue, nDigits, i );
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else if ( nLutSize == 5 )
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fprintf( pFile, ".INIT(32'h%08llx )) u_lut%0*d (", truthValue, nDigits, i );
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else // nLutSize == 6
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fprintf( pFile, ".INIT(64'h%016llx)) u_lut%0*d (", truthValue, nDigits, i );
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// Write LUT inputs - only the ones actually used by this LUT size
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for ( k = 0; k < nLutSize; k++ )
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{
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iFanin = Vec_IntEntry( vLeaves, k );
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if ( k > 0 )
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fprintf( pFile, ", " );
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fprintf( pFile, ".I%d(n%0*d)", k, nDigits, iFanin );
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}
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// Write LUT output
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fprintf( pFile, ", .O(n%0*d));\n", nDigits, i );
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}
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// Cleanup truth table computation
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Gia_ObjComputeTruthTableStop( p );
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Vec_IntFree( vLeaves );
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fprintf( pFile, "\n" );
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// Connect internal nodes to outputs (like regular &write_ver)
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Gia_ManForEachCo( p, pObj, i )
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{
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fprintf( pFile, " assign n%0*d = ", nDigits, Gia_ManCoIdToId(p, i) );
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GiaHie_PrintObjLit( pFile, Gia_ObjFaninId0p(p, pObj), Gia_ObjFaninC0(pObj), nDigits );
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fprintf( pFile, ";\n" );
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}
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fprintf( pFile, "\nendmodule\n" );
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fclose( pFile );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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@ -1314,6 +1503,30 @@ void Gia_WriteVerilog( char * pFileName, Gia_Man_t * pGia, int fUseGates, int fV
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GiaHie_DumpInterfaceAssigns( pGia, pFileName );
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}
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/**Function*************************************************************
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Synopsis [Writes mapped AIG as LUT6-based Verilog]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Gia_WriteMappedVerilog( char * pFileName, Gia_Man_t * pGia, int fVerbose )
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{
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(void)fVerbose;
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if ( pFileName == NULL || pGia == NULL )
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return;
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if ( !Gia_ManHasMapping(pGia) )
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{
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printf( "Cannot write LUT-based Verilog because AIG is not mapped.\n" );
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return;
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}
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GiaHie_DumpMappedLuts( pGia, pFileName );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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@ -35109,15 +35109,17 @@ usage:
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int Abc_CommandAbc9WriteVer( Abc_Frame_t * pAbc, int argc, char ** argv )
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{
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extern void Gia_WriteVerilog( char * pFileName, Gia_Man_t * pGia, int fUseGates, int fVerbose );
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extern void Gia_WriteMappedVerilog( char * pFileName, Gia_Man_t * pGia, int fVerbose );
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char * pFileSpec = NULL;
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Abc_Ntk_t * pNtkSpec = NULL;
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char * pFileName;
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char ** pArgvNew;
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int c, nArgcNew;
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int fUseGates = 0;
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int fUseLuts = 0;
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int fVerbose = 0;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "Sgvh" ) ) != EOF )
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while ( ( c = Extra_UtilGetopt( argc, argv, "Sglvh" ) ) != EOF )
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{
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switch ( c )
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{
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@ -35133,6 +35135,9 @@ int Abc_CommandAbc9WriteVer( Abc_Frame_t * pAbc, int argc, char ** argv )
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case 'g':
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fUseGates ^= 1;
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break;
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case 'l':
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fUseLuts ^= 1;
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break;
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case 'v':
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fVerbose ^= 1;
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break;
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@ -35157,7 +35162,21 @@ int Abc_CommandAbc9WriteVer( Abc_Frame_t * pAbc, int argc, char ** argv )
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Abc_Print( -1, "There is no AIG to write.\n" );
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return 1;
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}
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Gia_WriteVerilog( pFileName, pAbc->pGia, fUseGates, fVerbose );
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// Check if we should write LUT-based Verilog
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if ( fUseLuts || (Gia_ManHasMapping(pAbc->pGia) && !fUseGates) )
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{
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if ( !Gia_ManHasMapping(pAbc->pGia) )
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{
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Abc_Print( -1, "Cannot write LUT-based Verilog because AIG is not mapped.\n" );
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Abc_Print( -1, "Use \"&if\" to map the AIG first, or omit the -l flag.\n" );
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return 1;
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}
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Gia_WriteMappedVerilog( pFileName, pAbc->pGia, fVerbose );
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}
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else
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{
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Gia_WriteVerilog( pFileName, pAbc->pGia, fUseGates, fVerbose );
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}
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}
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else
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{
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@ -35179,13 +35198,15 @@ int Abc_CommandAbc9WriteVer( Abc_Frame_t * pAbc, int argc, char ** argv )
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return 0;
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usage:
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Abc_Print( -2, "usage: &write_ver [-S <file>] [-gvh] <file>\n" );
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Abc_Print( -2, "usage: &write_ver [-S <file>] [-glvh] <file>\n" );
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Abc_Print( -2, "\t writes hierarchical Verilog\n" );
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Abc_Print( -2, "\t-S file : file name for the original design (required when hierarchy is present)\n" );
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Abc_Print( -2, "\t-g : toggle output gates vs assign-statements [default = %s]\n", fUseGates? "gates": "assigns" );
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Abc_Print( -2, "\t-l : write LUT6-based Verilog for mapped AIGs [default = %s]\n", fUseLuts? "yes": "no" );
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Abc_Print( -2, "\t-v : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" );
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Abc_Print( -2, "\t-h : print the command usage\n");
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Abc_Print( -2, "\t<file> : the file name\n");
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Abc_Print( -2, "\tNote: When AIG is mapped and -l is not specified, LUT-based output is automatically used.\n");
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return 1;
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}
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