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5475 Commits

Author SHA1 Message Date
Carmine50 0ba2b7dae9 [CEC][SimGen][Clean codes] Removing unused parameters. 2024-12-24 11:49:17 +01:00
Carmine50 1a89f7ff63 [CEC][SimGen][CLI] Changed function name and help message. Added new option to specify file where to dump simulation vectors. Commented out too verbose information 2024-12-24 11:43:18 +01:00
Carmine50 463cf6a7df [CEC][SimGen][ABC Integration] Removed SAT solver calls and saving the simulation vectors in an internal data structure to pass to other functions. 2024-12-24 11:06:00 +01:00
Alan Mishchenko 14d46bfef8 Fixing big-endian problem if &fx and &deepsyn. 2024-12-23 20:26:00 -08:00
Alan Mishchenko 733fec328c Fixing big-endian problems in mfs2 and &mfs. 2024-12-23 20:04:21 -08:00
Alan Mishchenko cc894c5905 Deleting unused files. 2024-12-23 17:03:29 -08:00
Alan Mishchenko b81df1744f Removing unhelpful assertion. 2024-12-23 10:00:37 -08:00
Alan Mishchenko e21399f3bc Compiler warning. 2024-12-23 08:55:59 -08:00
alanminko 943bc0191c
Merge pull request #352 from wjrforcyber/conditional_jump 
Fix(&if -x): Conditional jump or move depends on uninitialised value(s)
 2024-12-23 08:52:54 -08:00
alanminko 01c6102ca7
Merge pull request #350 from wjrforcyber/put_bug_on_choice 
Fix(&put): &put bug with choices
 2024-12-23 08:52:29 -08:00
alanminko 733d2cd390
Merge pull request #348 from wjrforcyber/mem_leak 
Refactor(MemLeak): MemLeak fix in orchestrate
 2024-12-23 08:52:12 -08:00
wjrforcyber fdd66a8963
Fix(&if -x): Conditional jump or move depends on uninitialised value(s) 
From Valgrind:
==44570== Conditional jump or move depends on uninitialised value(s)
==44570==    at 0x9DEBA1: Dau_DsdRemoveBraces (dauMerge.c:563)
==44570==    by 0x9D1F53: Dau_DsdDecompose (dauDsd.c:1926)
==44570==    by 0x835523: If_DsdManCompute (ifDsd.c:2073)
==44570==    by 0x84177C: If_ObjPerformMappingAnd (ifMap.c:315)
==44570==    by 0x843720: If_ManPerformMappingRound (ifMap.c:667)
==44570==    by 0x813A01: If_ManPerformMappingComb (ifCore.c:126)
==44570==    by 0x813C88: If_ManPerformMapping (ifCore.c:91)
==44570==    by 0xE5F147: Gia_ManPerformMappingInt (giaIf.c:2503)
==44570==    by 0xE60976: Gia_ManPerformMapping (giaIf.c:2566)
==44570==    by 0x543605: Abc_CommandAbc9If (abc.c:41910)
==44570==    by 0x654739: CmdCommandDispatch (cmdUtils.c:157)
==44570==    by 0x64E0F2: Cmd_CommandExecute (cmdApi.c:210)
 2024-12-23 23:24:47 +08:00
Alan Mishchenko 42c2c54969 Fixing a big-endian issue in SOP manipulation and factoring. 2024-12-22 14:15:35 -08:00
Alan Mishchenko 207cfddaa8 Experiments with structural LUT cascade mapping. 2024-12-21 21:24:45 -08:00
Carmine50 ef8c35f95d [CEC][SimGen][LUT mapping] Adding option to consider an already mapped circuit before executing SimGen 2024-12-21 20:22:02 +01:00
Carmine50 8a1c28bf0f [CEC][SimGen][LUT mapping] Adding option to consider an already mapped circuit before executing SimGen 2024-12-21 20:15:40 +01:00
Carmine50 f407156de6 [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 16:19:47 +01:00
Carmine50 bd80d2e459 [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 16:04:45 +01:00
Carmine50 a6de82377d [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 15:57:47 +01:00
Carmine50 c104d9cb72 [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 14:26:54 +01:00
Carmine50 b999084ade [CEC][SimGen][CLI] Removed option of nMaxStep since it was unused 2024-12-19 18:12:28 +01:00
Carmine50 30af6f9868 [CEC][SimGen][CLI] Change name of command for simgen 2024-12-19 17:25:45 +01:00
Carmine50 87a3cafa44 [CEC][SimGen][Main Algo] Added main algorithm of SimGen and all necessary utility functions 2024-12-19 14:23:19 +01:00
Carmine50 0ea9929e65 [CEC][SimGen][Man new data struct] Added new variables in Gia_Man to save truth tables, MFFC infos and luts rankings for simgen. Modified also the function type to extract MFFC info 2024-12-19 14:22:26 +01:00
Carmine50 91dcfae020 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:56:12 +01:00
Carmine50 cbd4456805 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:53:44 +01:00
Carmine50 070ae52a46 [CEC][SimGen][Custom Parameters] Added custom parameters for SimGen CEC algo 2024-12-18 19:36:50 +01:00
Carmine50 99648e132f [CEC][SimGen][CLI] Added command line function to call SimGen main function. 2024-12-18 18:43:38 +01:00
wjrforcyber a8c65f1343
Fix(&put): &put bug with choices 
Related: #349
 2024-12-17 14:05:58 +08:00
Alan Mishchenko 8ba3d9b91c Trying anothe resource limit in scorr. 2024-12-14 13:44:18 -08:00
Alan Mishchenko 6754da13f2 Compiler warning. 2024-12-08 00:19:54 -08:00
wjrforcyber 7391a297bb
Refactor(MemLeak): MemLeak fix in orchestrate 2024-12-06 18:13:32 +08:00
Ethan Mahintorabi 01c9a65a47
map: Add Mio_Library_t* parameter to Abc_NtkMap 
This lets users of the ABC API call map without relying on the static
Mio_Library_t* in Abc_FrameReadLibGen.
 2024-12-02 06:55:42 +00:00
Alan Mishchenko 14168eb509 Updating command "rungen" to generate random functions. 2024-11-27 22:01:27 -08:00
Alan Mishchenko 1f3cf0aad9 Experiment with "scorr". 2024-11-17 15:44:32 -08:00
Alan Mishchenko 3aff0af0c5 Adding command for generating sorters. 2024-11-11 21:02:59 -08:00
Alan Mishchenko b5a76d8ba3 Compilation problem. 2024-11-10 19:30:24 -08:00
Alan Mishchenko f2e4ceb0e3 Update to "lutexact". 2024-11-10 19:12:40 -08:00
Alan Mishchenko aeb977286f Updates to LUT cascade synthesis. 2024-11-10 18:54:35 -08:00
Alan Mishchenko c787e32f86 Adding postiive minterm count for random functions generated by "lutexact". 2024-11-05 22:01:07 -08:00
Alan Mishchenko 091ff4e7a9 Adding generation of random functions to "lutexact" 2024-11-05 19:23:04 -08:00
Alan Mishchenko ecd948027e Fixing assertion failures in &put. 2024-10-23 14:49:57 +07:00
Alan Mishchenko cb2140dc0c Adding PI/PO name transfer after mapping+retiming. 2024-10-21 20:37:52 +07:00
alanminko 743f3a7bdd
Merge pull request #250 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2024-10-21 01:54:12 -07:00
alanminko 498ec539e6
Merge pull request #340 from aletempiac/acd_improvements 
Performance improvements to ACD
 2024-10-21 01:39:32 -07:00
alanminko a239dd8c0b
Merge pull request #328 from heshpdx/master 
Perf improvement in satsolver
 2024-10-21 01:38:40 -07:00
Alan Mishchenko f1773bd612 Procedure to detect node equivalences across two AIGs. 2024-10-21 15:15:08 +07:00
Alan Mishchenko 74e7c64662 Bug fix in &scorr 2024-10-21 13:16:29 +07:00
aletempiac baf4ddb16a Bug fix (just in the code; it does not affect the execution) 2024-10-15 19:04:49 +02:00
aletempiac d1f78b36cb Bug fix (just in the code; it does not affect the execution) 2024-10-15 19:00:45 +02:00
aletempiac 52c842b648 Cleaning code 2024-10-15 17:54:38 +02:00
aletempiac 46f2300b7b Performance improvements in ACD 2024-10-15 14:45:09 +02:00
Alan Mishchenko 707442e091 Bug fix in &scorr. 2024-10-08 10:01:29 +07:00
Alan Mishchenko 2e3384390a Updating "lutexact" to run on symmetric functions. 2024-10-07 14:10:02 +07:00
Alan Mishchenko af1de4fa9c Improved bit-blasting of some word-level operators. 2024-10-01 20:34:58 +07:00
Alan Mishchenko a78d358e1c Extending &funtrace to dump and load precomputed library. 2024-10-01 20:33:01 +07:00
Alan Mishchenko 6004b7b21e Adding API for inserting danginling flop. 2024-10-01 15:55:45 +07:00
Alan Mishchenko 4369321167 Bug fix. 2024-09-28 22:39:10 +02:00
alanminko 9539306436
Merge pull request #334 from mikesinouye/multilib 
Increase buffer size in filename append utility to support more liberty files.
 2024-09-22 20:48:15 -07:00
Yukio Miyasaka 35a8768c50 ttopt bugfix 2024-09-22 14:34:18 -07:00
Mike Inouye 8179c73e62 Try support for Windows again. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-09-18 23:46:28 +00:00
Mike Inouye 5bd52161cd Add #include <stdlib.h> for Windows build support. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-09-18 23:29:11 +00:00
Mike Inouye ee5acbbc01 Use <limits.h>'s PATH_MAX macro instead of fixed size. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-09-18 23:05:32 +00:00
Mike Inouye db735b632f Increase buffer size in filename append utility to support more liberty files. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-09-18 22:24:41 +00:00
Alan Mishchenko 9c152b71e9 Trasferring equivalence in the special-case usage of &scorr. 2024-09-12 18:11:59 -07:00
Alan Mishchenko 0d10253bd0 Another way of writing primary outputs in Verilog. 2024-09-06 06:27:53 -07:00
Alan Mishchenko 3ddd46131c Updating "read_lib" to output all gates when gain-based modeling is used. 2024-09-05 17:53:13 -07:00
Alan Mishchenko 3de73f2756 Updating internal cut manager to prefer cuts with high fanin fanout counts. 2024-09-05 13:27:17 -07:00
Alan Mishchenko 03d92930fa Updating &funtrace to trace function of the primary outputs of the AIG. 2024-09-03 17:16:48 -07:00
Mahesh Madhav ad8f8a2aab Convert the other divide to a multiply 2024-09-03 04:48:07 +00:00
Mahesh Madhav cd711089d7 Perf improvement in satsolver 
Switch one FP divide to an FP multiply (variable is constant).
Calculate ratio inside of verbosity clause, since that is where it is used.
 2024-09-03 04:30:14 +00:00
alanminko 5d6a568c9e
Merge pull request #327 from YosysHQ/povik/aiger-cell-mapping 
Save cell mapping as new 'M' AIGER extension
 2024-08-28 13:23:17 -07:00
Martin Povišer 786a39a294 Make casts explicit 2024-08-28 22:09:34 +02:00
Martin Povišer cb294bbebc Save cell mapping as new 'M' AIGER extension 2024-08-28 16:21:10 +02:00
wjrforcyber 252afb1521
Refactor(Resub): Clear mark A/B 2024-08-28 16:51:33 +08:00
wjrforcyber bcf292fdeb
Refactor(Resub): Clear markB at the beginning 2024-08-28 15:41:09 +08:00
Alan Mishchenko af77b80194 Regrouping recently added code. 2024-08-18 13:57:35 -07:00
Alan Mishchenko 5e35510e25 New APIs for AIG package. 2024-08-18 13:12:08 -07:00
Alan Mishchenko 03b786af99 Experiments with adder-based circuits. 2024-08-17 16:26:20 -07:00
Alan Mishchenko 732abf5b48 Compiler warnings. 2024-08-16 21:35:10 -07:00
Alan Mishchenko 2055b1b490 Adding an option to dump satisfying assignments into a BLIF file. 2024-08-14 14:41:35 -07:00
Alan Mishchenko c099e62032 Adding a switch to complement the primary outputs of an AIG. 2024-08-14 13:40:52 -07:00
Alan Mishchenko 1a62954eb8 Adding command to read ROM data. 2024-08-14 12:56:10 -07:00
Alan Mishchenko e2b7750d3b Experiments with bit-blasting. 2024-08-14 11:40:41 -07:00
Alan Mishchenko c2391686ea Adding BLIF dumping to "lutexact". 2024-08-13 20:03:18 -07:00
alanminko 324ceeaa08
Merge pull request #320 from YosysHQ/povik/revert-pdr 
Revert recent PDR changes
 2024-08-12 17:17:24 -07:00
Alan Mishchenko 81fcf8494e Updating "lutexact" to support single-rail LUT cascade. 2024-08-12 16:26:55 -07:00
Martin Povišer de8620d777 Revert "pdr -X to write CEXes immediately" 
This reverts commit e62e8ac528.
 2024-08-12 22:53:53 +02:00
Martin Povišer 39f6fbb052 Revert "Fix pdr timing output" 
This reverts commit c8d64b8682.
 2024-08-12 22:53:48 +02:00
Martin Povišer ec8419c84b Revert "Improved anytime pdr" 
This reverts commit 5444cf281c.
 2024-08-12 22:53:40 +02:00
Alan Mishchenko 807f6ddacf Experiments with detecting multipliers. 2024-08-10 19:24:00 -07:00
Alan Mishchenko e824cca0ca Fixing a serious bug in bit-blasting when multiplier argments have different bit-width. 2024-08-10 19:13:50 -07:00
Alan Mishchenko 71c4e23f97 Adding cut print-out in &funtrace. 2024-08-10 19:12:19 -07:00
Alan Mishchenko 35a1bbbdb4 Ongoing development related to Boolean decomposition. 2024-08-09 18:33:36 -07:00
Alan Mishchenko 4156a88dbb Extending &funtrace to trace functions found in an AIG. 2024-08-09 12:39:43 -07:00
alanminko 71b409b778
Merge pull request #319 from YosysHQ/povik/rm-buffering-asserts 
Remove extra asserts in buffering code
 2024-08-08 15:00:20 -07:00
alanminko 762a123edc
Merge pull request #318 from YosysHQ/povik/fix-atomic_store-call 
Fix types in call to atomic_store_explicit
 2024-08-08 15:00:05 -07:00
alanminko dce6e4899b
Merge pull request #317 from YosysHQ/povik/fix-transfer-timing 
Handle edge case in Gia_ManTransferTiming
 2024-08-08 14:59:49 -07:00
alanminko 0129b4c60a
Merge pull request #316 from YosysHQ/povik/yosyshq-commands 
Pull command changes from YosysHQ fork
 2024-08-08 14:59:31 -07:00
alanminko e6b36cb5da
Merge pull request #315 from YosysHQ/povik/yosyshq-build 
Pull build-related changes from YosysHQ fork
 2024-08-08 14:58:42 -07:00