mirror of https://github.com/YosysHQ/abc.git
Merge pull request #319 from YosysHQ/povik/rm-buffering-asserts
Remove extra asserts in buffering code
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commit
71b409b778
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@ -345,7 +345,7 @@ Abc_Obj_t * Abc_SclAddOneInv( Bus_Man_t * p, Abc_Obj_t * pObj, Vec_Ptr_t * vFano
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SC_Cell * pCellNew;
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Abc_Obj_t * pFanout, * pInv;
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float Target = SC_CellPinCap(p->pInv, 0) * Gain;
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float LoadWirePrev, LoadWireThis, LoadNew, Load = 0;
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float LoadWirePrev, LoadWireThis, Load = 0;
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int Limit = Abc_MinInt( p->pPars->nDegree, Vec_PtrSize(vFanouts) );
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int i, iStop;
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Bus_SclCheckSortedFanout( vFanouts );
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@ -384,8 +384,7 @@ Abc_Obj_t * Abc_SclAddOneInv( Bus_Man_t * p, Abc_Obj_t * pObj, Vec_Ptr_t * vFano
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Vec_IntSetEntry( p->pNtk->vGates, Abc_ObjId(pInv), pCellNew->Id );
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// set departure and load
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Abc_NtkComputeNodeDeparture( pInv, p->pPars->Slew );
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LoadNew = Abc_NtkComputeNodeLoad( p, pInv );
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assert( LoadNew - Load < 1 && Load - LoadNew < 1 );
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Abc_NtkComputeNodeLoad( p, pInv );
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// set fanout info for the inverter
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Bus_SclObjSetCin( pInv, SC_CellPinCap(pCellNew, 0) );
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Bus_SclObjSetETime( pInv, Abc_NtkComputeEdgeDept(pInv, 0, p->pPars->Slew) );
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@ -400,7 +399,7 @@ void Abc_SclBufSize( Bus_Man_t * p, float Gain )
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Abc_Obj_t * pObj, * pFanout;
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abctime clk = Abc_Clock();
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int i, k, nObjsOld = Abc_NtkObjNumMax(p->pNtk);
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float GainGate, GainInv, Load, LoadNew, Cin, DeptMax = 0;
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float GainGate, GainInv, Load, Cin, DeptMax = 0;
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GainGate = p->pPars->fAddBufs ? (float)pow( (double)Gain, (double)2.0 ) : Gain;
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GainInv = p->pPars->fAddBufs ? (float)pow( (double)Gain, (double)2.0 ) : Gain;
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Abc_NtkForEachObjReverse( p->pNtk, pObj, i )
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@ -453,8 +452,7 @@ void Abc_SclBufSize( Bus_Man_t * p, float Gain )
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if ( Abc_ObjFaninNum(pFanout) == 0 )
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Abc_ObjAddFanin( pFanout, pObj );
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Bus_SclObjSetLoad( pObj, 0 );
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LoadNew = Abc_NtkComputeNodeLoad( p, pObj );
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assert( LoadNew - Load < 1 && Load - LoadNew < 1 );
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Abc_NtkComputeNodeLoad( p, pObj );
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}
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if ( Abc_ObjIsCi(pObj) )
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continue;
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