luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
6,266 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

904 Commits

Author SHA1 Message Date
Alan Mishchenko d54cbda229 Multi-output gate mapper. 2026-05-10 09:52:16 -07:00
Alan Mishchenko f3157272ae Initial support of multi-output gates in sizing. 2026-05-08 16:03:24 -07:00
Alan Mishchenko eaa8496b42 Streamlining support for multi-output gates 2026-05-08 00:45:46 -07:00
Alan Mishchenko 6aaf0db1e1 Fixing the required time problem. 2026-03-25 10:03:26 -07:00
Alan Mishchenko 60e0303e3a Fix a mismatch in cut selection. 2026-03-24 20:16:09 -07:00
Alan Mishchenko 3881f2de37 Updated to &sprove. 2026-03-23 17:34:59 -07:00
Alan Mishchenko cf5aef3889 Fix compiler problems. 2026-03-10 22:26:43 -07:00
Alan Mishchenko fa5029da95 Updates to &if mapper. 2026-03-10 22:19:37 -07:00
Drew Lewis ee40e40d09 Have the buffer grow with a 2x factor to avoid O(n^2) work when reading big files. 
Signed-off-by: Drew Lewis <cannada@google.com>
 2026-03-02 22:22:27 +00:00
Alan Mishchenko 90be4816ce Updating delay trace for LUT mapping. 2026-02-08 22:50:12 -08:00
Miodrag Milanovic f2ae808236 MINGW proper pthread handling 2026-01-29 09:28:21 +01:00
Alan Mishchenko 309282601e Experiments with LUT mapping. 2025-11-17 21:37:51 -08:00
Alan Mishchenko 5273eab9f7 Fixing compilation problem. 2025-11-01 11:14:37 -07:00
Alan Mishchenko 7c6b779327 Supporting programmable cell libraries. 2025-11-01 01:23:30 -07:00
Alan Mishchenko a9d62d845d Experiments with LUT mapping. 2025-11-01 01:21:37 -07:00
Alan Mishchenko 6034f6621b Changes to cut dumping. 2025-10-30 22:14:18 -07:00
Alan Mishchenko 18f6464ec7 Experiments with LUT mapping. 2025-10-24 16:57:55 -07:00
Alan Mishchenko 3a1efd48f7 Enabling multiple LUT libraries. 2025-10-24 11:46:55 -07:00
Alan Mishchenko 4c6b082463 Reusing switch "-j" in "if" and "&if". 2025-10-24 10:59:56 -07:00
Alan Mishchenko 6fb4f739b0 Suppress a warning about uninitialized variable. 2025-10-24 10:58:38 -07:00
Alan Mishchenko 5adfd0030d Silencing benign assertion failure (Issue #428) 2025-08-29 18:41:38 -07:00
alanminko 4dfa49774f
Merge pull request #438 from chenjunhao0315/master 
rewire support timing-constraint
 2025-08-29 10:55:59 -07:00
jiunhaochen 4f29be9046 rewire support timing-constraint 2025-08-27 00:56:43 +08:00
Martin Povišer 3455f423d0 Fix capacitance unit parsing 
Fix the liberty parser to handle "capacitive_load_unit (1,fF)".
Previously this input would produce a corrupted internal representation
for the library as there would be an extra value written on line 944.
 2025-08-26 12:05:05 +02:00
Alan Mishchenko 279217b73d Updating procedures to dump cut info. 2025-08-18 22:00:43 -07:00
Alan Mishchenko 0e4a080779 Enabling "if" to dump the cut and truth table info. 2025-08-16 16:32:29 -07:00
Alan Mishchenko c5ceff2bee Dumping a binary file with truth tables in "if". 2025-08-12 16:00:26 -07:00
MyskYko f443db4a24 fix amap -m 2025-06-16 10:27:33 -07:00
Mike Inouye a4064b8b73 Prevent merged scl filename size from growing unbounded, which limits upper bound of files loaded. 2025-05-30 18:14:47 +00:00
Alan Mishchenko 57966de4b4 Adding flag to skip two-output cells in "read_lib". 2025-05-14 17:01:48 -07:00
Alan Mishchenko d34821e768 Skipping cells with more than two outputs in "read_lib". 2025-05-14 14:17:05 -07:00
Alan Mishchenko a42e6ecd23 Fixing a bug in "read_lib". 2025-05-09 17:13:40 -07:00
Alan Mishchenko dcf9079507 Extending "stochmap" to work for AIGs. 2025-04-15 21:56:24 -07:00
Alan Mishchenko aaba1b9a5f Experiments with mapping. 2025-03-13 20:59:17 -07:00
Alan Mishchenko b09305204d Minor bug fixes. 2025-03-10 20:13:53 -07:00
Alan Mishchenko ecc27e80dc Adding support for the genlib library file name. 2025-03-10 14:37:29 -07:00
Alan Mishchenko 3dc77bbe1c Bug fix in "stochmap". 2025-03-09 23:52:03 -07:00
Alan Mishchenko 38ba7d78aa Experiment with mapping. 2025-03-09 15:42:25 -07:00
wjrforcyber 5632bb8892
Fix(Pointer): Fix the wrong value passed to size 
Signed-off-by: wjrforcyber <wjrforcyber@163.com>
 2025-03-01 21:03:51 +08:00
alanminko 57e504db7b
Merge pull request #362 from wjrforcyber/gz_lib_support 
Feat(read_lib): Gz lib format support
 2025-02-15 05:30:24 +07:00
alanminko a2e4c153c9
Merge pull request #255 from phsauter/fix-scl-regression 
Fix Segfault in scl
 2025-02-15 05:28:25 +07:00
wjrforcyber 303907ec0c
Update(read_lib): Remove redundant header 2025-01-21 15:58:31 +08:00
wjrforcyber adf9b4e7fb
Feat(read_lib): Support .gz file 2025-01-21 15:54:38 +08:00
aletempiac baf4ddb16a Bug fix (just in the code; it does not affect the execution) 2024-10-15 19:04:49 +02:00
aletempiac d1f78b36cb Bug fix (just in the code; it does not affect the execution) 2024-10-15 19:00:45 +02:00
aletempiac 52c842b648 Cleaning code 2024-10-15 17:54:38 +02:00
aletempiac 46f2300b7b Performance improvements in ACD 2024-10-15 14:45:09 +02:00
Alan Mishchenko 3ddd46131c Updating "read_lib" to output all gates when gain-based modeling is used. 2024-09-05 17:53:13 -07:00
Alan Mishchenko 732abf5b48 Compiler warnings. 2024-08-16 21:35:10 -07:00
alanminko 71b409b778
Merge pull request #319 from YosysHQ/povik/rm-buffering-asserts 
Remove extra asserts in buffering code
 2024-08-08 15:00:20 -07:00