mirror of https://github.com/YosysHQ/abc.git
Experiments with LUT mapping.
This commit is contained in:
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309282601e
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@ -1583,11 +1583,11 @@ void Gia_AigerWriteS( Gia_Man_t * pInit, char * pFileName, int fWriteSymbols, in
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{
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unsigned char CellId = (unsigned char)Vec_StrEntry(p->vConfigs2, i);
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if ( CellId == 0 )
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i += 4; // 1 byte CellId + 2 bytes truth table + 1 padding
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i += 7; // 1 byte CellId + 4 bytes mapping + 2 bytes truth table
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else if ( CellId == 1 )
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i += 12; // 1 byte CellId + 4 bytes mapping + 4 bytes truth tables + 3 padding
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i += 12; // 1 byte CellId + 7 bytes mapping + 4 bytes truth tables
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else if ( CellId == 2 )
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i += 12; // 1 byte CellId + 5 bytes mapping + 4 bytes truth tables + 2 padding
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i += 14; // 1 byte CellId + 9 bytes mapping + 4 bytes truth tables
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else
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assert( 0 ); // Unknown cell type
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nInstances++;
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@ -1619,15 +1619,15 @@ void Gia_AigerWriteS( Gia_Man_t * pInit, char * pFileName, int fWriteSymbols, in
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// Write cell type 0 (LUT4)
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Gia_FileWriteBufferSize( pFile, 0 ); // CellId
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fwrite( pCell0, 1, strlen(pCell0) + 1, pFile );
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Gia_FileWriteBufferSize( pFile, 4 ); // 1 byte CellId + 2 bytes truth table, rounded to 4
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Gia_FileWriteBufferSize( pFile, 7 ); // 1 byte CellId + 4 bytes mapping + 2 bytes truth table
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// Write cell type 1 (S44)
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Gia_FileWriteBufferSize( pFile, 1 ); // CellId
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fwrite( pCell1, 1, strlen(pCell1) + 1, pFile );
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Gia_FileWriteBufferSize( pFile, 12 ); // 1 byte CellId + 4 bytes mapping + 4 bytes truth tables, rounded to 12
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Gia_FileWriteBufferSize( pFile, 12 ); // 1 byte CellId + 7 bytes mapping + 4 bytes truth tables
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// Write cell type 2 (9-input)
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Gia_FileWriteBufferSize( pFile, 2 ); // CellId
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fwrite( pCell2, 1, strlen(pCell2) + 1, pFile );
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Gia_FileWriteBufferSize( pFile, 12 ); // 1 byte CellId + 5 bytes mapping + 4 bytes truth tables (LUT4s only), rounded to 12
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Gia_FileWriteBufferSize( pFile, 14 ); // 1 byte CellId + 9 bytes mapping + 4 bytes truth tables
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// Write total instances
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Gia_FileWriteBufferSize( pFile, nInstances );
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// Write instance data as raw bytes
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@ -2016,73 +2016,73 @@ void Gia_ManConfigPrint( word Truth4, word z, int nLeaves )
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***********************************************************************/
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void Gia_ManFromIfGetConfig2( Vec_Str_t * vConfigs2, If_Man_t * pIfMan, word * pTruth, int nLeaves )
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{
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int i, CellId, nBytes;
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int i, CellId;
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int startPos = Vec_StrSize(vConfigs2);
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// Determine cell type based on the number of leaves and configuration
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if ( nLeaves <= 4 )
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if ( nLeaves <= 4 ) // 7 bytes = 1 byte CellId + 4 bytes mapping + 2 bytes truth table
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{
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// Cell type 0: Simple LUT4
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CellId = 0;
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nBytes = 3; // 1 byte CellId + 2 bytes truth table (16 bits)
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// Write CellId
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Vec_StrPush( vConfigs2, (char)CellId );
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// Write mapping
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for ( i = 0; i < nLeaves; i++ )
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Vec_StrPush( vConfigs2, 2+i );
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for ( ; i < 4; i++ )
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Vec_StrPush( vConfigs2, 0 );
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// Write truth table (16 bits for LUT4)
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word Truth = pTruth[0];
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Vec_StrPush( vConfigs2, (char)(Truth & 0xFF) );
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Vec_StrPush( vConfigs2, (char)((Truth >> 8) & 0xFF) );
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// Pad to 4-byte boundary
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while ( (Vec_StrSize(vConfigs2) - startPos) % 4 != 0 )
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Vec_StrPush( vConfigs2, 0 );
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//Gia_ManConfigPrint( Truth, 0, pCutBest->nLeaves );
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Vec_StrPush( vConfigs2, (char)(Truth & 0xFF) );
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assert( startPos + 7 == Vec_StrSize(vConfigs2) );
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//Gia_ManConfigPrint( Truth, 0, nLeaves );
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}
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else
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else // 12 bytes = 1 byte CellId + 7 bytes mapping + 4 bytes truth tables
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{
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word z = If_CutPerformDeriveJ( pIfMan, (unsigned *)pTruth, nLeaves, nLeaves, NULL, 1 );
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//Gia_ManConfigPrint( 0, z, pCutBest->nLeaves );
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//Gia_ManConfigPrint( 0, z, nLeaves );
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if ( ((z >> 63) & 1) == 0 )
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{
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CellId = 1;
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unsigned char mappingBytes[4] = {0};
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// Write CellId
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Vec_StrPush( vConfigs2, (char)CellId );
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// Write input mappings for first LUT4 (4 inputs)
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// Write input mapping
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for ( i = 0; i < 4; i++ )
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{
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int v = (int)((z >> (16 + (i << 2))) & 7);
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if ( v == 6 && nLeaves == 5 )
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mappingBytes[i / 2] |= (0 << ((i % 2) * 4)); // constant 0
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Vec_StrPush( vConfigs2, 0 );
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else
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mappingBytes[i / 2] |= ((v+2) << ((i % 2) * 4)); // leaf v (direct mapping)
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Vec_StrPush( vConfigs2, 2+v );
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}
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Vec_StrPush( vConfigs2, (char)mappingBytes[0] );
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Vec_StrPush( vConfigs2, (char)mappingBytes[1] );
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// Write input mappings for second LUT4 (4 inputs)
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mappingBytes[0] = mappingBytes[1] = 0;
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int iSpecial = -1;
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for ( i = 0; i < 4; i++ )
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{
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int v = (int)((z >> (48 + (i << 2))) & 7);
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if ( v == 6 && nLeaves == 5 )
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mappingBytes[i / 2] |= (0 << ((i % 2) * 4)); // constant 0
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Vec_StrPush( vConfigs2, 0 );
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else if ( v != 7 )
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Vec_StrPush( vConfigs2, 2+v );
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else if ( v == 7 )
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mappingBytes[i / 2] |= ((7+2) << ((i % 2) * 4)); // output of first LUT at index N+2 where N=7
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else
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mappingBytes[i / 2] |= ((v+2) << ((i % 2) * 4)); // leaf v (direct mapping)
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iSpecial = i;
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}
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Vec_StrPush( vConfigs2, (char)mappingBytes[0] );
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Vec_StrPush( vConfigs2, (char)mappingBytes[1] );
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// Transform the truth table
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assert( iSpecial >= 0 );
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word Truth = (z >> 32) & 0xFFFF;
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Truth = Abc_Tt6Stretch( Truth, 4 );
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for ( int v = iSpecial; v < 3; v++ )
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Truth = Abc_Tt6SwapAdjacent( Truth, v );
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// Write truth tables
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word Truth1 = z & 0xFFFF;
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word Truth2 = (z >> 32) & 0xFFFF;
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Vec_StrPush( vConfigs2, (char)(Truth1 & 0xFF) );
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//word Truth2 = (z >> 32) & 0xFFFF;
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word Truth2 = Truth & 0xFFFF;
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Vec_StrPush( vConfigs2, (char)((Truth1 >> 8) & 0xFF) );
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Vec_StrPush( vConfigs2, (char)(Truth2 & 0xFF) );
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Vec_StrPush( vConfigs2, (char)(Truth1 & 0xFF) );
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Vec_StrPush( vConfigs2, (char)((Truth2 >> 8) & 0xFF) );
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// Pad to 4-byte boundary
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while ( (Vec_StrSize(vConfigs2) - startPos) % 4 != 0 )
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Vec_StrPush( vConfigs2, 0 );
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Vec_StrPush( vConfigs2, (char)(Truth2 & 0xFF) );
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assert( startPos + 12 == Vec_StrSize(vConfigs2) );
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}
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else
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else // 14 bytes = 1 byte CellId + 9 bytes mapping + 4 bytes truth tables
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{
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CellId = 2;
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int Pla2Var[9];
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@ -2090,39 +2090,22 @@ void Gia_ManFromIfGetConfig2( Vec_Str_t * vConfigs2, If_Man_t * pIfMan, word * p
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If_PermUnpack( (unsigned)(z >> 32), Pla2Var );
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// Write CellId
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Vec_StrPush( vConfigs2, (char)CellId );
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// Write input mappings (9 inputs, 4 bits each, packed)
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unsigned char mappingByte = 0;
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int bitPos = 0;
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// Write input mapping
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for ( i = 0; i < 9; i++ )
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{
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int v;
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if ( Pla2Var[i] == 9 ) // constant 0
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v = 0;
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else // leaf index
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v = Pla2Var[i] + 2;
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if ( bitPos == 0 ) {
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mappingByte = v & 0xF;
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bitPos = 4;
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}
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else {
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mappingByte |= (v & 0xF) << 4;
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Vec_StrPush( vConfigs2, (char)mappingByte );
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bitPos = 0;
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}
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}
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// Push last byte if needed
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if ( bitPos != 0 )
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Vec_StrPush( vConfigs2, (char)mappingByte );
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if ( Pla2Var[i] == 9 )
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Vec_StrPush( vConfigs2, 0 );
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else
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Vec_StrPush( vConfigs2, Pla2Var[i] + 2 );
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}
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// Write truth tables for the two LUT4s only (MUX is structural, not a LUT)
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word Truth1 = z & 0xFFFF;
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word Truth2 = (z >> 16) & 0xFFFF;
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Vec_StrPush( vConfigs2, (char)(Truth1 & 0xFF) );
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Vec_StrPush( vConfigs2, (char)((Truth1 >> 8) & 0xFF) );
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Vec_StrPush( vConfigs2, (char)(Truth2 & 0xFF) );
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Vec_StrPush( vConfigs2, (char)(Truth1 & 0xFF) );
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Vec_StrPush( vConfigs2, (char)((Truth2 >> 8) & 0xFF) );
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// Pad to 4-byte boundary
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while ( (Vec_StrSize(vConfigs2) - startPos) % 4 != 0 )
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Vec_StrPush( vConfigs2, 0 );
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Vec_StrPush( vConfigs2, (char)(Truth2 & 0xFF) );
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assert( startPos + 14 == Vec_StrSize(vConfigs2) );
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}
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}
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}
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@ -911,12 +911,15 @@ void If_ManConfigPrint( unsigned char * pConfigData, int nLeaves )
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printf( "[%4d] ", Count++ ); // Print instance number
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if ( CellId == 0 )
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{
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assert( nLeaves <= 4 );
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// Extract 16-bit truth table
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word Truth = ((word)pConfigData[2] << 8) | pConfigData[1];
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word Truth = ((word)pConfigData[5] << 8) | pConfigData[6];
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printf( "%04lX{", (unsigned long)Truth );
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// Print as simple {abcd} since it's just a direct LUT4
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for ( i = 0; i < nLeaves && i < 4; i++ )
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for ( i = 0; i < nLeaves; i++ )
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printf( "%c", 'a' + i );
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for ( ; i < 4; i++ )
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printf( "%c", '0' );
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printf( "}" );
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// Pad with spaces if less than 4 inputs
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for ( i = nLeaves; i < 4; i++ )
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@ -926,11 +929,11 @@ void If_ManConfigPrint( unsigned char * pConfigData, int nLeaves )
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else if ( CellId == 1 )
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{
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// First LUT4
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word Truth1 = ((word)pConfigData[6] << 8) | pConfigData[5];
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word Truth1 = ((word)pConfigData[8] << 8) | pConfigData[9];
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printf( "h=%04lX{", (unsigned long)Truth1 );
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for ( i = 0; i < 4; i++ )
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{
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int v = (pConfigData[1 + i/2] >> ((i%2) * 4)) & 0xF;
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int v = pConfigData[1+i];
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if ( v == 0 )
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printf( "0");
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else if ( v == 1 )
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@ -942,11 +945,11 @@ void If_ManConfigPrint( unsigned char * pConfigData, int nLeaves )
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}
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printf( "} ");
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// Second LUT4
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word Truth2 = ((word)pConfigData[8] << 8) | pConfigData[7];
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word Truth2 = ((word)pConfigData[10] << 8) | pConfigData[11];
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printf( "i=%04lX{", (unsigned long)Truth2 );
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for ( i = 0; i < 4; i++ )
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for ( i = 4; i < 7; i++ )
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{
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int v = (pConfigData[3 + i/2] >> ((i%2) * 4)) & 0xF;
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int v = pConfigData[1+i];
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if ( v == 0 )
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printf( "0");
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else if ( v == 1 )
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@ -958,32 +961,16 @@ void If_ManConfigPrint( unsigned char * pConfigData, int nLeaves )
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else
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printf( "?");
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}
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printf( "} [Cell %d, %d leaves]\n", CellId, nLeaves );
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printf( "h} [Cell %d, %d leaves]\n", CellId, nLeaves );
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}
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else if ( CellId == 2 )
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{
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// Extract 9 input mappings
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int inputs[9];
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int bitPos = 0;
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for ( i = 0; i < 9; i++ )
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{
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if ( bitPos == 0 )
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{
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inputs[i] = pConfigData[1 + i/2] & 0xF;
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bitPos = 4;
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}
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else
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{
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inputs[i] = (pConfigData[1 + i/2] >> 4) & 0xF;
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bitPos = 0;
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}
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}
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// First LUT4
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word Truth1 = ((word)pConfigData[7] << 8) | pConfigData[6];
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word Truth1 = ((word)pConfigData[10] << 8) | pConfigData[11];
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printf( "j=%04lX{", (unsigned long)Truth1 );
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for ( i = 0; i < 4; i++ )
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{
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int v = inputs[i];
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int v = pConfigData[1+i];
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if ( v == 0 )
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printf( "0");
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else if ( v == 1 )
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@ -995,11 +982,11 @@ void If_ManConfigPrint( unsigned char * pConfigData, int nLeaves )
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}
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printf( "} ");
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// Second LUT4
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word Truth2 = ((word)pConfigData[9] << 8) | pConfigData[8];
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word Truth2 = ((word)pConfigData[12] << 8) | pConfigData[13];
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printf( "k=%04lX{", (unsigned long)Truth2 );
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for ( i = 4; i < 8; i++ )
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{
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int v = inputs[i];
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int v = pConfigData[1+i];
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if ( v == 0 )
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printf( "0");
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else if ( v == 1 )
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@ -1012,7 +999,7 @@ void If_ManConfigPrint( unsigned char * pConfigData, int nLeaves )
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printf( "} ");
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// final node
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printf( "l=<");
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int v = inputs[8];
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int v = pConfigData[1+8];
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if ( v == 0 )
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printf( "0");
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else if ( v == 1 )
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@ -1087,11 +1074,11 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
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if ( CellId == 0 )
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{
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// Extract 16-bit truth table
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word Truth = ((word)pConfigData[2] << 8) | pConfigData[1];
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word Truth = ((word)pConfigData[5] << 8) | pConfigData[6];
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Truth = Abc_Tt6Stretch( Truth, 4 );
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extern int Kit_TruthToGia( Gia_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory, Vec_Int_t * vLeaves, int fHash );
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Gia_ManObj(p, iLut)->Value = Kit_TruthToGia( pNew, (unsigned *)&Truth, Vec_IntSize(vLeaves), vCover, vLeaves, 1 );
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bytePos += 4; // 1 byte CellId + 2 bytes truth table + 1 padding
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bytePos += 7; // 1 byte CellId + 4 bytes mapping + 2 bytes truth table
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}
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else if ( CellId == 1 )
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{
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@ -1101,7 +1088,7 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
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Vec_IntClear( vLeavesTemp );
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for ( i = 0; i < 4; i++ )
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{
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int v = (pConfigData[1 + i/2] >> ((i%2) * 4)) & 0xF;
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int v = pConfigData[1+i];
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if ( v == 0 )
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Vec_IntPush( vLeavesTemp, 0 ); // constant 0
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else if ( v == 1 )
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@ -1111,58 +1098,41 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
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else
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assert( 0 ); // Invalid value
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}
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word Truth1 = ((word)pConfigData[6] << 8) | pConfigData[5];
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word Truth1 = ((word)pConfigData[8] << 8) | pConfigData[9];
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Truth1 = Abc_Tt6Stretch( Truth1, 4 );
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extern int Kit_TruthToGia( Gia_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory, Vec_Int_t * vLeaves, int fHash );
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iObjLit1 = Kit_TruthToGia( pNew, (unsigned *)&Truth1, Vec_IntSize(vLeavesTemp), vCover, vLeavesTemp, 1 );
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// Second LUT4 - extract inputs and truth table
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Vec_IntClear( vLeavesTemp );
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for ( i = 0; i < 4; i++ )
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for ( i = 4; i < 7; i++ )
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{
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int v = (pConfigData[3 + i/2] >> ((i%2) * 4)) & 0xF;
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int v = pConfigData[1+i];
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if ( v == 0 )
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Vec_IntPush( vLeavesTemp, 0 ); // constant 0
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else if ( v == 1 )
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Vec_IntPush( vLeavesTemp, 1 ); // constant 1
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else if ( v >= 2 && v < 2 + Vec_IntSize(vLeaves) )
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Vec_IntPush( vLeavesTemp, Vec_IntEntry(vLeaves, v - 2) ); // leaf (v-2)
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else if ( v == 9 ) // N+2 where N=7 (number of S44 inputs)
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Vec_IntPush( vLeavesTemp, iObjLit1 ); // output of first LUT (internal connection)
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else
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assert( 0 ); // Invalid value
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}
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word Truth2 = ((word)pConfigData[8] << 8) | pConfigData[7];
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Vec_IntPush( vLeavesTemp, iObjLit1 ); // output of first LUT (internal connection)
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word Truth2 = ((word)pConfigData[10] << 8) | pConfigData[11];
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Truth2 = Abc_Tt6Stretch( Truth2, 4 );
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iObjLit2 = Kit_TruthToGia( pNew, (unsigned *)&Truth2, Vec_IntSize(vLeavesTemp), vCover, vLeavesTemp, 1 );
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Gia_ManObj(p, iLut)->Value = iObjLit2;
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Vec_IntFree( vLeavesTemp );
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bytePos += 12; // 1 byte CellId + 4 bytes mapping + 4 bytes truth tables + 3 padding
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bytePos += 12; // 1 byte CellId + 7 bytes mapping + 4 bytes truth tables
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}
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else if ( CellId == 2 )
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{
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Vec_Int_t * vLeavesTemp = Vec_IntAlloc( 4 );
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int iObjLit1, iObjLit2, iObjLit3;
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// Extract 9 input mappings (4 bits each, packed)
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int inputs[9];
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int bitPos = 0;
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for ( i = 0; i < 9; i++ )
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{
|
||||
if ( bitPos == 0 )
|
||||
{
|
||||
inputs[i] = pConfigData[1 + i/2] & 0xF;
|
||||
bitPos = 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
inputs[i] = (pConfigData[1 + i/2] >> 4) & 0xF;
|
||||
bitPos = 0;
|
||||
}
|
||||
}
|
||||
// First LUT4 (inputs 0-3)
|
||||
Vec_IntClear( vLeavesTemp );
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
int v = inputs[i];
|
||||
int v = pConfigData[1+i];
|
||||
if ( v == 0 )
|
||||
Vec_IntPush( vLeavesTemp, 0 ); // constant 0
|
||||
else if ( v == 1 )
|
||||
|
|
@ -1172,7 +1142,7 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
|
|||
else
|
||||
assert( 0 ); // Invalid value
|
||||
}
|
||||
word Truth1 = ((word)pConfigData[7] << 8) | pConfigData[6];
|
||||
word Truth1 = ((word)pConfigData[10] << 8) | pConfigData[11];
|
||||
Truth1 = Abc_Tt6Stretch( Truth1, 4 );
|
||||
extern int Kit_TruthToGia( Gia_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory, Vec_Int_t * vLeaves, int fHash );
|
||||
iObjLit1 = Kit_TruthToGia( pNew, (unsigned *)&Truth1, Vec_IntSize(vLeavesTemp), vCover, vLeavesTemp, 1 );
|
||||
|
|
@ -1180,7 +1150,7 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
|
|||
Vec_IntClear( vLeavesTemp );
|
||||
for ( i = 4; i < 8; i++ )
|
||||
{
|
||||
int v = inputs[i];
|
||||
int v = pConfigData[1+i];
|
||||
if ( v == 0 )
|
||||
Vec_IntPush( vLeavesTemp, 0 ); // constant 0
|
||||
else if ( v == 1 )
|
||||
|
|
@ -1190,12 +1160,12 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
|
|||
else
|
||||
assert( 0 ); // Invalid value
|
||||
}
|
||||
word Truth2 = ((word)pConfigData[9] << 8) | pConfigData[8];
|
||||
word Truth2 = ((word)pConfigData[12] << 8) | pConfigData[13];
|
||||
Truth2 = Abc_Tt6Stretch( Truth2, 4 );
|
||||
iObjLit2 = Kit_TruthToGia( pNew, (unsigned *)&Truth2, Vec_IntSize(vLeavesTemp), vCover, vLeavesTemp, 1 );
|
||||
// MUX (select is input 8) - structural implementation
|
||||
int iSelectLit;
|
||||
int v = inputs[8];
|
||||
int v = pConfigData[1+8];
|
||||
if ( v == 0 )
|
||||
iSelectLit = 0; // constant 0 select
|
||||
else if ( v == 1 )
|
||||
|
|
@ -1207,7 +1177,7 @@ void * If_ManDeriveGiaFromCells2( void * pGia )
|
|||
iObjLit3 = Gia_ManHashMux( pNew, iSelectLit, iObjLit2, iObjLit1 );
|
||||
Gia_ManObj(p, iLut)->Value = iObjLit3;
|
||||
Vec_IntFree( vLeavesTemp );
|
||||
bytePos += 12; // 1 byte CellId + 5 bytes mapping + 4 bytes truth tables + 2 padding
|
||||
bytePos += 14; // 1 byte CellId + 9 bytes mapping + 4 bytes truth tables
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue