luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,718 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

1382 Commits

Author SHA1 Message Date
Alan Mishchenko 35b816dd57 Enabling cofactoring in the mapper. 2014-08-06 14:18:20 -07:00
Alan Mishchenko 1d9d6814ee Enabling ISOP-based minimization in 'collapse' if EXDC is available. 2014-08-04 10:53:08 -07:00
Alan Mishchenko edba505d9d Profiling code for SOP/DSD/LMS balancing. 2014-08-02 17:01:48 -07:00
Alan Mishchenko 62bc45d1fb Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, such as [7:7], which seems to help in some cases. 2014-08-02 17:00:24 -07:00
Alan Mishchenko 7fb1954268 Small changes. 2014-07-29 22:49:10 -07:00
Alan Mishchenko 6a69a9139c Adding support for standard-cell mapping. 2014-07-28 11:31:31 -07:00
Alan Mishchenko 704b4bad6b Generating abstraction of standard cell library. 2014-07-26 16:46:45 -07:00
Alan Mishchenko 7d81490fe6 Generating abstraction of standard cell library. 2014-07-25 20:02:56 -07:00
Alan Mishchenko 2cdc5ab850 Bug fix in 'print_gates' due to the mix-up of the inverter. 2014-07-22 17:23:48 -07:00
Alan Mishchenko ba29267563 Small changes. 2014-07-21 22:43:08 -07:00
Alan Mishchenko c0aa9b6a5d Adding new command &sopb for resource-aware SOP balancing. 2014-07-21 13:49:25 -07:00
Alan Mishchenko ea73401db5 Updates and changes to several packages. 2014-07-20 22:11:00 -07:00
Alan Mishchenko 4a861d868c Small changes in several packages. 2014-07-17 09:47:07 -07:00
Alan Mishchenko c58b57e2b4 Improvements to profiling and printing statistics. 2014-07-09 20:22:51 -07:00
Alan Mishchenko b389f2054b Improvements to false path detection. 2014-07-08 23:51:20 -07:00
Alan Mishchenko afcec52a49 Improvements to representation of choices. 2014-07-01 13:05:09 -07:00
Alan Mishchenko 6bc381baa3 Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_Ntk_t representing an AIG, by skipping object ID number 0 reserved for the constant node. 2014-06-30 15:28:53 -07:00
Alan Mishchenko 1586d96c3e Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_Ntk_t representing an AIG, by skipping object ID number 0 reserved for the constant node. 2014-06-30 15:21:47 -07:00
Alan Mishchenko 55404ca1af Changes and improvements to different packages. 2014-06-28 14:31:01 -07:00
Alan Mishchenko 933b749676 Changes and improvements to different packages. 2014-06-28 14:25:38 -07:00
Alan Mishchenko a68ec38df1 Changes and improvements to different packages. 2014-06-26 09:51:53 -07:00
Alan Mishchenko 2edf2a970e Improvements to power-aware mapping. 2014-06-23 18:05:51 -07:00
Alan Mishchenko f79d8e4b04 Improvements to CNF generation. 2014-06-23 14:50:46 -07:00
Alan Mishchenko 44d9c7e543 Improvements to CNF generation. 2014-06-23 13:11:59 -07:00
Alan Mishchenko f93e524421 Added command &mux_profile. 2014-06-22 17:08:21 -07:00
Alan Mishchenko 13dd4eeb59 Experiments with balancing. 2014-06-22 00:50:07 -07:00
Alan Mishchenko 1e76ebdf3b New tools for profiling verification miters. 2014-06-20 17:51:35 -07:00
Alan Mishchenko f04d32732b Added quick GIG parser. 2014-06-19 21:16:30 -07:00
Alan Mishchenko f98f610bab Added delay-oriented balancing to unmapping in &st. 2014-06-19 19:12:10 -07:00
Alan Mishchenko 85e23c8459 Various changes to enable better CNF generation. 2014-06-17 21:00:51 -07:00
Alan Mishchenko a03a726de2 Bug fix in writing latch init values in 'write_aiger'. 2014-06-17 14:21:28 -07:00
Alan Mishchenko dd867b404a Added transformation of CEX after 'fix_aig' and checking of transformed CEXes using 'testcex -a'. 2014-06-17 12:21:48 -07:00
Alan Mishchenko e20364896e Bug fix in CEC generation after rarity simulation and few small changes. 2014-06-16 16:46:39 -07:00
Alan Mishchenko 2340d279bd Adding support of multi-output problems in &splitprove. 2014-06-15 22:58:25 -07:00
Alan Mishchenko e2637595f8 Updates and bug fixes. 2014-06-15 16:28:05 -07:00
Alan Mishchenko cf993a9d90 Adding more features to the synthesis script &syn2. 2014-06-14 19:03:05 -07:00
Alan Mishchenko 0ac22c9e1d Specializing some truth-table functions to 6 inputs. 2014-06-14 18:29:19 -07:00
Alan Mishchenko fcdd9148b4 Various modifications. 2014-06-12 21:27:14 -07:00
Alan Mishchenko 865f6fd43f Enabling switching activity. 2014-06-12 11:28:47 -07:00
Alan Mishchenko 082e5dc1b0 Integrating recent changes. 2014-06-12 11:08:54 -07:00
Alan Mishchenko 0d1a1c4624 Adding switch to &st to convert to larger gates. 2014-06-11 22:21:55 -07:00
Alan Mishchenko 93d89eaaeb Various modifications. 2014-06-10 21:31:10 -07:00
Alan Mishchenko 6ce9ac9bbd Skip 'scorr' when the network has no primary inputs. 2014-06-09 08:14:45 -07:00
Alan Mishchenko 3c6def2915 Adding print-out to &splitprove to see impact of cof variable on AIG size. 2014-06-07 13:14:23 -07:00
Alan Mishchenko 2d38fc1608 Adding print-out to &splitprove to see impact of cof variable on AIG size. 2014-06-07 13:04:03 -07:00
Alan Mishchenko 8a341c200f Adding a feature to collapse hierarhical AIGs. 2014-06-05 19:15:40 -07:00
Alan Mishchenko 78e09e9119 Correcting switching activity computation. 2014-06-05 17:00:04 -07:00
Alan Mishchenko c5b620b9bf Fixed printout of in the hierarchy log file. 2014-06-05 11:17:32 -07:00
Alan Mishchenko 3abc3fb4ff Fixed printout of in the hierarchy log file. 2014-06-05 10:57:04 -07:00
Alan Mishchenko 54d3c1ab42 Fixed printout of in the hierarchy log file. 2014-06-05 10:46:43 -07:00