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4896 Commits

Author SHA1 Message Date
alanminko 0fc13478b8
Merge pull request #133 from twier/inv_get_name_mangling_fix 
Fix name-mangling behavior of inv_get
 2021-08-19 09:48:58 -07:00
Alan Mishchenko 77760dd8ac Extending &trim to trim structurally equivalent primary outputs. 2021-08-19 09:48:46 -07:00
Tobias Wiersema b82a7f4677 Add comment to Wlc_NtkGetInv about vNamesIn's role 2021-08-19 18:01:38 +02:00
Tobias Wiersema d55e8fab82 Fix typo inifity -> infinity in inv_get help 2021-08-19 17:57:54 +02:00
Tobias Wiersema ca710b3dda Add inv_get -f to read flop names from GIA 2021-08-19 17:57:19 +02:00
Alan Mishchenko 4da6cc8904 Improving AIG to Verilog converter. 2021-08-17 16:52:29 -07:00
Alan Mishchenko e9b487666d Suggested changes to collect and pass timing information (unused variable). 2021-08-12 18:27:40 -07:00
Alan Mishchenko 0deb8bf632 Suggested changes to collect and pass timing information (compiler issues). 2021-08-12 18:26:37 -07:00
Alan Mishchenko e8ac47641f Suggested changes to collect and pass timing information. 2021-08-12 18:25:00 -07:00
Alan Mishchenko 99ab99bfa6 Making &cec support the miter circuit. 2021-08-05 15:05:59 -07:00
Alan Mishchenko ddc574a954 Supporting simple operators in NDR. 2021-08-05 14:01:55 -07:00
Alan Mishchenko ab29dad7f4 Adding node ordering options to command &dfs. 2021-08-05 11:07:16 -07:00
Alan Mishchenko ae98e57caf Bug fix. 2021-08-03 10:14:10 -07:00
Alan Mishchenko dd87461ac9 Experiments with LUT mapping for small functions. 2021-08-02 16:48:52 -07:00
Alan Mishchenko 5f8d4e72d1 Experiments with LUT mapping for small functions. 2021-08-02 16:46:56 -07:00
Alan Mishchenko 03bb1e49bf Experiments with LUT mapping for small functions. 2021-08-01 12:14:38 -07:00
Alan Mishchenko 4cf906d2fc Experiments with LUT mapping for small functions. 2021-08-01 12:13:27 -07:00
Alan Mishchenko e162a26197 Allow retiming to skip some logic. 2021-07-31 22:46:47 -07:00
Alan Mishchenko 692dd76319 Upgrading choice computation. 2021-07-31 15:34:46 -07:00
Alan Mishchenko d925e4802c Experiments with cofactoring. 2021-07-31 11:30:19 -07:00
Alan Mishchenko a162b1f47a Experimental simulation commands. 2021-07-25 14:11:34 -07:00
Alan Mishchenko 62180f3576 Command to move CI/CO names. 2021-07-16 13:46:41 -07:00
Alan Mishchenko 6e5a797a6d Command to move CI/CO names. 2021-07-16 13:44:38 -07:00
Alan Mishchenko d9aeaade3b Several unrelated changes. 2021-07-15 18:23:04 -07:00
Alan Mishchenko 3e67d167f5 Experiments with LUT mapping for small functions. 2021-07-13 19:05:02 -07:00
Alan Mishchenko be14c39740 Experiments with MUX decomposition. 2021-07-11 00:04:59 -07:00
Alan Mishchenko 9fac6c7a8b Experiments with CEC. 2021-07-10 10:50:33 -07:00
Alan Mishchenko fdc9e89d66 Simple AIGER reader/writer. 2021-07-09 11:53:50 -07:00
Alan Mishchenko 4116e13b5e Experiments with MUX decomposition. 2021-07-08 21:54:46 -07:00
Alan Mishchenko 96b9192c78 Experiments with MUX decomposition. 2021-07-08 21:54:07 -07:00
Alan Mishchenko 5a135c8799 Experiments with MUX decomposition. 2021-07-08 21:42:15 -07:00
Alan Mishchenko 4c90af0f10 Potential upgrade to 'dsec'. 2021-06-25 07:05:38 -07:00
Alan Mishchenko 28ba2c5213 Adding place holder file for resub experiments. 2021-06-24 19:18:28 -07:00
Alan Mishchenko b4f099c511 Experiments with LUT mapping for small functions. 2021-06-19 19:26:41 -07:00
Alan Mishchenko db3f5b6d0b Experiments with cut computation. 2021-06-08 11:39:42 -07:00
Alan Mishchenko 7d18d6b7aa Experiments with cut computation. 2021-06-05 17:48:12 -07:00
Alan Mishchenko 84ec53fbf9 Disabled special handling of 2-input LUTs. 2021-06-03 08:39:30 -07:00
Alan Mishchenko 7fcbffd2af Disabled special handling of 2-input LUTs. 2021-06-02 18:57:22 -07:00
Alan Mishchenko 8889ccb18c Updating LUT synthesis code. 2021-05-26 23:25:08 -07:00
Alan Mishchenko 49078ffebf Updating LUT synthesis code. 2021-05-25 23:12:30 -07:00
Alan Mishchenko d35b05859c Adding command &extract. 2021-05-18 16:42:16 -07:00
Alan Mishchenko 91a2eafc7a Fixing memory leak in the SAT sweeper. 2021-05-16 20:39:47 -07:00
Alan Mishchenko 93849685b3 Updating LUT synthesis code. 2021-05-16 20:35:55 -07:00
Alan Mishchenko 0ce11851bc Updating LUT synthesis code. 2021-05-16 20:33:53 -07:00
Alan Mishchenko 610a3d3fc2 Adding switch muxes -a to create networks of ADDs. 2021-05-15 13:28:06 -07:00
Alan Mishchenko ed13c6d4d2 Updating LUT synthesis code. 2021-05-11 17:45:20 -07:00
Alan Mishchenko e6a47c3e41 Disable cube-sort when deriving SOPs. 2021-05-11 15:54:43 -07:00
Alan Mishchenko aa9fe1f240 Updating LUT synthesis code. 2021-05-11 15:04:15 -07:00
Alan Mishchenko 76bed2055c Updating LUT synthesis code. 2021-05-08 20:10:44 -07:00
Alan Mishchenko 17476146ca Fixing mismatch in &cec -x which should return undecided rather than non-equivalent when the miter cannot be reduced to constant 0. 2021-05-08 19:07:10 -07:00