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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-16 12:10:11 +08:00
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User-Documentation.md

@ -37,6 +37,7 @@ After the parameters, connect the ports of the top module to your design. Below
| i_ddr3_clk_90 | clock required only if ODELAY_SUPPORTED = 0, otherwise can be left unconnected. Has a period of `DDR3_CLK_PERIOD` with 90° phase shift. | | i_ddr3_clk_90 | clock required only if ODELAY_SUPPORTED = 0, otherwise can be left unconnected. Has a period of `DDR3_CLK_PERIOD` with 90° phase shift. |
| i_rst_n | Active-low synchronous reset for the entire DDR3 controller and PHY | | i_rst_n | Active-low synchronous reset for the entire DDR3 controller and PHY |
It is recommended to generate all these clocks from a single PLL or clock-generator.
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