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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-16 12:06:40 +08:00
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User-Documentation.md

@ -69,7 +69,7 @@ After main wishbone port are the **second-wishbone ports**. This interface is on
Next are the **DDR3 I/O ports**, these will be connected directly to the top-level pins of your design thus port-names must match what is indicated on your constraint file. You do not need to understand what each DDR3 I/O ports does but if you're curious, details on each DDR3 I/O pins are described on _2.10 Pinout Description_ from [JEDEC DDR3 doc (page 13)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf).
Finally are the debug ports, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored.
Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored.
## Connecting to Top-Level DDR3 I/O Pins