From 5f29cb20138df20590b2da69b4ede205873f8c3f Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 16 Nov 2023 12:10:11 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 1 + 1 file changed, 1 insertion(+) diff --git a/User-Documentation.md b/User-Documentation.md index de65798..348923a 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -37,6 +37,7 @@ After the parameters, connect the ports of the top module to your design. Below | i_ddr3_clk_90 | clock required only if ODELAY_SUPPORTED = 0, otherwise can be left unconnected. Has a period of `DDR3_CLK_PERIOD` with 90° phase shift. | | i_rst_n | Active-low synchronous reset for the entire DDR3 controller and PHY | +It is recommended to generate all these clocks from a single PLL or clock-generator. ***