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UberDDR3
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Opensource DDR3 Controller
18 Commits 6 Branches 0 Tags 65 MiB
Verilog 58.7%
SystemVerilog 21.3%
Tcl 15.6%
Makefile 1.7%
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Angelo Jacobo fa5fcc2615
use a 4-bit counter plus a 4-bit mask for tracking delay in every bank 
this is the optimized delay-tracking mechanism on which the 32-bit shift regs is replaced by a 4-bit counter plus a 4-bit mask. This uses lower resources but still able to track the delays and the exact slot number where the delay is already satisfied (hence no added latency)
 		2023-03-30 18:17:46 +08:00
rtl use a 4-bit counter plus a 4-bit mask for tracking delay in every bank 2023-03-30 18:17:46 +08:00
LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-03-13 14:40:46 +08:00
ddr3_controller.sby removed parameter file "ddr3_parameters.vh" 2023-03-09 18:16:01 +08:00
run.sh include directory on iverilog command 2023-03-02 20:20:14 +08:00

README.md

DDR3_Controller

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