Opensource DDR3 Controller

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Angelo Jacobo fa3f5e0d65 use 32-bit shift reg for tracking delay inside every bank There are 4 delays being tracked (delay_before_precharge, delay_before_activate, delay_before_read, and delay_before_write) and 8 banks, that means 32x4x8 = 1024 bits needed for this tracking delay mechanism (totally wasteful!)		2023-03-30 18:14:09 +08:00
rtl	use 32-bit shift reg for tracking delay inside every bank	2023-03-30 18:14:09 +08:00
LICENSE	changed license to Apache 2.0	2023-03-23 20:18:46 +08:00
README.md	Update README.md	2023-03-13 14:40:46 +08:00
ddr3_controller.sby	removed parameter file "ddr3_parameters.vh"	2023-03-09 18:16:01 +08:00
run.sh	include directory on iverilog command	2023-03-02 20:20:14 +08:00

DDR3_Controller

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