4.2 KiB
4.2 KiB
DDR3_Controller
🚧 👷♂️ 👷♂️ UNDER CONSTRUCTION 👷♂️ 👷♂️ 🚧
Sequential Read
Sequential Read then Sequential Write
Random Access
Sequential Read Until Next Bank
PHY Interface
WRITE OPERATION
Sequential Write
BITSLIP_DQS_TRAIN STATE:
MPR_READ STATE:
BITSLIP_DQ_TRAIN STATE:
Sequential Read:
PER LANE READ CALIBRATION
AFTER READ CALIBRATION
LANES NOT IN SYNC
SAMPLE READ 1
SAMPLE READ 2 (UNIFORM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)
SAMPLE READ 3 (UNIFORM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)
SAMPLE READ 4 (RANDOM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)
SAMPLE READ 5 (RANDOM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)
Autofpga "make autofpga"
Implementation!!
Successful Synthesis-to-Bitstream Generation