UberDDR3/README.md

# DDR3_Controller
# :construction: :construction_worker_man: :construction_worker_man:  UNDER CONSTRUCTION :construction_worker_man: :construction_worker_man: :construction: 

## Sequential Read
![image](https://user-images.githubusercontent.com/87559347/230342721-c5a575db-0518-4771-a5e6-7fa7e3044273.png)  

## Sequential Read then Sequential Write
![image](https://user-images.githubusercontent.com/87559347/230336798-619a629d-9f7d-431f-8887-a05965b1c70a.png)


## Random Access
![image](https://user-images.githubusercontent.com/87559347/230362722-256dafff-04c1-4052-b664-6b3d234d9089.png)

## Sequential Read Until Next Bank
![image](https://user-images.githubusercontent.com/87559347/230366265-a10b22b1-8113-46f7-9980-f8938a0b4a0c.png)

# PHY Interface    
## WRITE OPERATION   

![image](https://user-images.githubusercontent.com/87559347/233351111-10434e18-4c5c-4751-95c5-536288c514ed.png)

## Sequential Write


![image](https://user-images.githubusercontent.com/87559347/233395320-66a16ad8-1d56-4850-b82e-39abda92366f.png)

## BITSLIP_DQS_TRAIN STATE:

![image](https://user-images.githubusercontent.com/87559347/234852977-21656591-5a52-4916-8546-caa929f273cc.png)

## MPR_READ STATE:
![image](https://user-images.githubusercontent.com/87559347/234854161-3d8ed26a-3ddf-4cf6-a440-616361ee5715.png)

## BITSLIP_DQ_TRAIN STATE: 
![image](https://user-images.githubusercontent.com/87559347/234854620-39d95493-ecc8-4b8f-b391-0f532fff5760.png)


## Sequential Read:
![image](https://user-images.githubusercontent.com/87559347/234856001-ab9056fe-cee1-47b6-a7b7-347ee5138c4f.png)

## PER LANE READ CALIBRATION 
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/827c9097-dc13-47ad-b8c3-3a505108a327)


## AFTER READ CALIBRATION
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/02128baa-19d0-4268-9cfd-93ab70ae2288)

## LANES NOT IN SYNC
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/a4ccc6fb-3a07-4f09-adc5-b7d45b430323)

## SAMPLE READ 1 
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/37147480-339b-41fb-8e00-77218c4c7ad1)

## SAMPLE READ 2 (UNIFORM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/7b27e335-0854-49fe-bd68-9b18aae21abd)

## SAMPLE READ 3 (UNIFORM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/330aa43e-baaa-4201-bc46-990662c18156)

## SAMPLE READ 4 (RANDOM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/cfe39227-d5ea-4ccd-b943-3ee07dbb9b23)

## SAMPLE READ 5 (RANDOM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/cf50d5d1-91bb-4581-9d5e-bd4f05aee53d)


## Autofpga "make autofpga"
![Screenshot from 2023-05-18 11-49-19](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/0144ca4c-616e-420c-b464-6e71bf540041)


## Implementation!!
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/763eea4b-a330-4f45-8d0a-672c5643b5dc)

![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/ef9af6cc-3a9a-47ec-a45c-f21d30edc9d5)

## Successful Synthesis-to-Bitstream Generation
![Screenshot from 2023-05-25 19-38-39](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/eb89a6a3-2aab-4c1b-8fbc-f9ecfe508ebd)
![Screenshot from 2023-05-25 19-38-50](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/d6bf96db-6aa5-48b0-a9e4-2288306c0ef7)

## Model Test  

![Screenshot from 2023-06-01 18-49-13](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/cfc3c4bb-f66b-4464-9ab3-0084531fdcca)

![Screenshot from 2023-06-08 09-10-27](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/e2da7d28-bf0e-4b19-9ef0-0c928ff902bf)

![Screenshot from 2023-06-08 09-58-16](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/6bc4845c-cfe4-463a-a4d5-910bbf65edc8)

![Screenshot from 2023-06-10 22-40-12](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/9d304b48-bd28-4167-88b8-cda3339ec861)

![Screenshot from 2023-06-20 20-44-34](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/dac4ee44-d3f4-441f-b6c4-61f62b4bea46)
Update README.md 2023-03-02 13:32:12 +01:00			`# DDR3_Controller`
Update README.md 2023-03-13 07:40:46 +01:00			`# :construction: :construction_worker_man: :construction_worker_man: UNDER CONSTRUCTION :construction_worker_man: :construction_worker_man: :construction:`
Update README.md 2023-04-06 11:31:23 +02:00
Update README.md 2023-04-06 11:34:05 +02:00			`## Sequential Read`
Update README.md 2023-04-06 11:54:16 +02:00			`![image](https://user-images.githubusercontent.com/87559347/230342721-c5a575db-0518-4771-a5e6-7fa7e3044273.png)`
Update README.md 2023-04-06 11:34:05 +02:00
Update README.md 2023-04-06 11:31:23 +02:00			`## Sequential Read then Sequential Write`
Update README.md 2023-04-06 11:34:05 +02:00			`![image](https://user-images.githubusercontent.com/87559347/230336798-619a629d-9f7d-431f-8887-a05965b1c70a.png)`

Update README.md 2023-04-06 11:31:23 +02:00
Update README.md 2023-04-06 13:22:22 +02:00			`## Random Access`
			`![image](https://user-images.githubusercontent.com/87559347/230362722-256dafff-04c1-4052-b664-6b3d234d9089.png)`
Update README.md 2023-04-06 13:41:57 +02:00
			`## Sequential Read Until Next Bank`
			`![image](https://user-images.githubusercontent.com/87559347/230366265-a10b22b1-8113-46f7-9980-f8938a0b4a0c.png)`
Update README.md 2023-04-20 13:20:47 +02:00
			`# PHY Interface`
			`## WRITE OPERATION`

			`![image](https://user-images.githubusercontent.com/87559347/233351111-10434e18-4c5c-4751-95c5-536288c514ed.png)`

Update README.md 2023-04-20 13:59:55 +02:00			`## Sequential Write`

Update README.md 2023-04-20 16:20:44 +02:00
			`![image](https://user-images.githubusercontent.com/87559347/233395320-66a16ad8-1d56-4850-b82e-39abda92366f.png)`
Update README.md 2023-04-27 13:48:59 +02:00
			`## BITSLIP_DQS_TRAIN STATE:`

			`![image](https://user-images.githubusercontent.com/87559347/234852977-21656591-5a52-4916-8546-caa929f273cc.png)`

Update README.md 2023-04-27 13:56:43 +02:00			`## MPR_READ STATE:`
			`![image](https://user-images.githubusercontent.com/87559347/234854161-3d8ed26a-3ddf-4cf6-a440-616361ee5715.png)`

			`## BITSLIP_DQ_TRAIN STATE:`
			`![image](https://user-images.githubusercontent.com/87559347/234854620-39d95493-ecc8-4b8f-b391-0f532fff5760.png)`


Update README.md 2023-04-27 14:02:37 +02:00			`## Sequential Read:`
			`![image](https://user-images.githubusercontent.com/87559347/234856001-ab9056fe-cee1-47b6-a7b7-347ee5138c4f.png)`
Update README.md 2023-04-27 13:48:59 +02:00
Update README.md 2023-05-11 12:03:30 +02:00			`## PER LANE READ CALIBRATION`
Update README.md 2023-05-11 13:07:17 +02:00			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/827c9097-dc13-47ad-b8c3-3a505108a327)`

Update README.md 2023-05-11 12:03:30 +02:00
			`## AFTER READ CALIBRATION`
			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/02128baa-19d0-4268-9cfd-93ab70ae2288)`
Update README.md 2023-05-11 12:24:12 +02:00
			`## LANES NOT IN SYNC`
			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/a4ccc6fb-3a07-4f09-adc5-b7d45b430323)`
Update README.md 2023-05-11 12:50:59 +02:00
Update README.md 2023-05-11 12:58:25 +02:00			`## SAMPLE READ 1`
Update README.md 2023-05-11 12:50:59 +02:00			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/37147480-339b-41fb-8e00-77218c4c7ad1)`

Update README.md 2023-05-11 13:12:16 +02:00			`## SAMPLE READ 2 (UNIFORM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)`
Update README.md 2023-05-11 12:58:25 +02:00			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/7b27e335-0854-49fe-bd68-9b18aae21abd)`

Update README.md 2023-05-11 13:12:16 +02:00			`## SAMPLE READ 3 (UNIFORM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)`
Update README.md 2023-05-11 13:23:11 +02:00			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/330aa43e-baaa-4201-bc46-990662c18156)`
Update README.md 2023-05-11 13:22:34 +02:00
Update README.md 2023-05-11 13:36:56 +02:00			`## SAMPLE READ 4 (RANDOM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)`
Update README.md 2023-05-11 13:22:34 +02:00			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/cfe39227-d5ea-4ccd-b943-3ee07dbb9b23)`

Update README.md 2023-05-11 13:36:56 +02:00			`## SAMPLE READ 5 (RANDOM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)`
			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/cf50d5d1-91bb-4581-9d5e-bd4f05aee53d)`

Update README.md 2023-05-18 05:51:19 +02:00
			`## Autofpga "make autofpga"`
			`![Screenshot from 2023-05-18 11-49-19](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/0144ca4c-616e-420c-b464-6e71bf540041)`
Update README.md 2023-05-22 13:59:17 +02:00

			`## Implementation!!`
			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/763eea4b-a330-4f45-8d0a-672c5643b5dc)`

			`![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/ef9af6cc-3a9a-47ec-a45c-f21d30edc9d5)`

Update README.md 2023-05-25 13:41:51 +02:00			`## Successful Synthesis-to-Bitstream Generation`
			`![Screenshot from 2023-05-25 19-38-39](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/eb89a6a3-2aab-4c1b-8fbc-f9ecfe508ebd)`
			`![Screenshot from 2023-05-25 19-38-50](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/d6bf96db-6aa5-48b0-a9e4-2288306c0ef7)`

Update README.md 2023-06-01 13:27:25 +02:00			`## Model Test`
Update README.md 2023-05-22 13:59:17 +02:00
Update README.md 2023-06-01 13:27:25 +02:00			`![Screenshot from 2023-06-01 18-49-13](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/cfc3c4bb-f66b-4464-9ab3-0084531fdcca)`
Update README.md 2023-06-08 08:16:27 +02:00
			`![Screenshot from 2023-06-08 09-10-27](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/e2da7d28-bf0e-4b19-9ef0-0c928ff902bf)`

			`![Screenshot from 2023-06-08 09-58-16](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/6bc4845c-cfe4-463a-a4d5-910bbf65edc8)`

Update README.md 2023-06-15 12:54:42 +02:00			`![Screenshot from 2023-06-10 22-40-12](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/9d304b48-bd28-4167-88b8-cda3339ec861)`
Update README.md 2023-06-08 08:16:27 +02:00
Update README.md 2023-06-22 14:01:01 +02:00			`![Screenshot from 2023-06-20 20-44-34](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/dac4ee44-d3f4-441f-b6c4-61f62b4bea46)`