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UberDDR3
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Opensource DDR3 Controller
16 Commits 5 Branches 0 Tags 96 MiB
Verilog 57.7%
SystemVerilog 21.8%
Tcl 16%
Makefile 1.7%
Shell 1.4%
Other 1.4%
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Angelo Jacobo 73e5f6b3de
added begin-end in short if-else statement 		2023-03-23 20:35:37 +08:00
rtl added begin-end in short if-else statement 2023-03-23 20:35:37 +08:00
LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-03-13 14:40:46 +08:00
ddr3_controller.sby removed parameter file "ddr3_parameters.vh" 2023-03-09 18:16:01 +08:00
run.sh include directory on iverilog command 2023-03-02 20:20:14 +08:00

README.md

DDR3_Controller

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