Angelo Jacobo 98ed92a65b added testbench for a single ddr3 device sim		2023-06-03 14:28:55 +08:00
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DDR3 SDRAM Verilog Model	added testbench for a single ddr3 device sim	2023-06-03 14:28:55 +08:00
ddr3_controller.v	fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk	2023-06-01 19:18:41 +08:00
ddr3_phy.v	added phy for generating differential o_ddr3_clk	2023-05-29 21:51:48 +08:00
ddr3_top.v	added o_ddr3_clk port	2023-05-29 21:48:44 +08:00