Opensource DDR3 Controller

controller ddr3 ddr3-controller ddr3-phy fpga memory-controller phy verilog

Go to file

Angelo Jacobo 38109d8297 added initial RTLs		2023-03-02 20:04:37 +08:00
rtl	added initial RTLs	2023-03-02 20:04:37 +08:00
LICENSE	Initial commit	2023-03-02 19:44:58 +08:00
README.md	Initial commit	2023-03-02 19:44:58 +08:00

README.md

DDR3_Controller