UberDDR3/testbench/models
AngeloJacobo e5bd0d74c3 use SIM_MODEL directive to use models during vivado simulation 2025-05-25 09:03:16 +08:00
..
IDELAYCTRL_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
IDELAYE2_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
IOBUFDS_DCIEN_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
IOBUFDS_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
IOBUF_DCIEN_model.v use SIM_MODEL directive to use models during vivado simulation 2025-05-25 09:03:16 +08:00
IOBUF_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
ISERDESE2_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
OBUFDS_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
OBUF_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
ODELAYE2_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00
OSERDESE2_model.v moved verilog models to model/ 2025-05-24 17:31:55 +08:00