62 lines
1.6 KiB
Verilog
Executable File
62 lines
1.6 KiB
Verilog
Executable File
`timescale 1 ps / 1 ps
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module IOBUF_model (
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output O,
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inout IO,
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input I,
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input T
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);
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parameter IBUF_LOW_PWR = "TRUE";
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parameter SLEW = "SLOW";
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`ifdef NO_TEST_MODEL
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parameter TEST_MODEL = 0;
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`else
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parameter TEST_MODEL = 1;
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`endif
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bufif0 T1 (IO, I, T);
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buf B1 (O, IO);
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generate
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if(TEST_MODEL == 1) begin
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reg unequal = 0;
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wire O_test, IO_test;
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bufif0 (IO_test, IO, 1'b0);
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IOBUF #(
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.IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
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.SLEW("FAST") // Specify the output slew rate
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) IOBUF_test_model (
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.O(O_test),// Buffer output
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.IO(IO_test), // Buffer inout port (connect directly to top-level port)
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.I(I), // Buffer input
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.T(T) // 3-state enable input, high=read, low=write
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);
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always @* begin
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#1;
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if((O !== O_test) && ($time > 500_000)) begin
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$display("IOBUF MODEL O does not match: time = %t", $time);
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unequal <= 1;
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$stop;
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end
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if((IO != IO_test) && ($time > 500_000)) begin
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$display("IOBUF MODEL IO does not match: time = %t", $time);
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unequal <= 1;
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$stop;
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end
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end
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initial begin
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$display("---------------------------------------- TESTING IOBUF Model ----------------------------------------");
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end
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end
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endgenerate
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endmodule
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