50 lines
1.3 KiB
Verilog
Executable File
50 lines
1.3 KiB
Verilog
Executable File
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`timescale 1 ps/1 ps
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module OBUFDS_model (
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output wire O,
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output wire OB,
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input wire I
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);
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`ifdef NO_TEST_MODEL
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parameter TEST_MODEL = 0;
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`else
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parameter TEST_MODEL = 1;
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`endif
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bufif0 (O, I, 1'b0);
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notif0 (OB, I, 1'b0);
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generate
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if(TEST_MODEL == 1) begin
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wire O_test, OB_test;
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reg unequal = 0;
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OBUFDS OBUFDS_test_model (
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.O(O_test), // Diff_p output (connect directly to top-level port)
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.OB(OB_test), // Diff_n output (connect directly to top-level port)
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.I(I) // Buffer input
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);
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always @* begin
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#1;
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if((O !== O_test) && ($time > 500_000)) begin
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$display("OBUFDS MODEL O does not match: time = %t", $time);
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unequal <= 1;
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$stop;
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end
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if((OB !== OB_test) && ($time > 500_000)) begin
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$display("OBUFDS MODEL OB does not match: time = %t", $time);
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unequal <= 1;
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$stop;
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end
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end
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initial begin
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$display("---------------------------------------- TESTING OBUFDS Model ----------------------------------------");
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end
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end
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endgenerate
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endmodule
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