AngeloJacobo 3c4c4b9f83 optimize stage1/2 stall logic, optimize size of registers (delay_before_*, added_read_pipe*, delay_read_pipe), register huge conditions, explicit removal of unused states)		2025-12-31 14:35:04 +08:00
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axi	update UberDDR3 AXI for Vivado custom IP	2025-02-16 14:53:05 +08:00
ecc	Revert "add self-refresh option, passing Simulation, ongoing formal"	2024-11-23 11:43:05 +08:00
ecp5_phy	added support for DLL_OFF and Lattice ECP5 PHY	2025-04-19 13:24:20 +08:00
spd	added simulation and project demo with XADC	2025-01-12 14:55:43 +08:00
ddr3_controller.v	optimize stage1/2 stall logic, optimize size of registers (delay_before_*, added_read_pipe*, delay_read_pipe), register huge conditions, explicit removal of unused states)	2025-12-31 14:35:04 +08:00
ddr3_phy.v	use SIM_MODEL directive to use models during vivado simulation	2025-05-25 09:03:16 +08:00
ddr3_top.v	set default BIST_MODE to 1 for shorter bring up	2025-04-19 13:37:58 +08:00