7 Commits

Author	SHA1	Message	Date
Angelo Jacobo	fa3f5e0d65	use 32-bit shift reg for tracking delay inside every bank ... There are 4 delays being tracked (delay_before_precharge, delay_before_activate, delay_before_read, and delay_before_write) and 8 banks, that means 32x4x8 = 1024 bits needed for this tracking delay mechanism (totally wasteful!)	2023-03-30 18:14:09 +08:00
Angelo Jacobo	73e5f6b3de	added begin-end in short if-else statement	2023-03-23 20:35:37 +08:00
Angelo Jacobo	97092cf869	added logic for refresh sequence and bank access	2023-03-23 20:17:12 +08:00
Angelo Jacobo	adb21070d4	used :retab and fixed tab spacing	2023-03-09 18:14:58 +08:00
Angelo Jacobo	c5d387fa24	added reset sequence and formal assertions ... - completed (mostly) the reset sequence - added formal assertions and cover statements for reset sequence logic - moved all parameters to this file - fixed port widths - converted IO ports to ANSI	2023-03-09 18:06:53 +08:00
Angelo Jacobo	3633613c47	Update ddr3_controller.v	2023-03-02 20:12:28 +08:00
Angelo Jacobo	38109d8297	added initial RTLs	2023-03-02 20:04:37 +08:00