2c73f38f99
added debug port and max function for int type
2023-08-01 15:58:58 +08:00
d5f1d600ea
resolve verilator warnings and add option YOSYS for not using input real in functions
2023-07-24 17:27:17 +08:00
7142dd9cdb
added more registers and formal assertions to wb2
2023-07-19 18:46:36 +08:00
97e740139f
resolved vivado warnings
2023-07-17 21:38:20 +08:00
019722bc70
resolve warnings and errors from verilator linting
2023-07-16 08:17:55 +08:00
47766cb8e8
added wishbone 2 and formally verified it
2023-07-13 18:41:25 +08:00
5904a4910d
shortened formal depth from 9 to 7
2023-07-09 09:34:03 +08:00
b03ca1864f
shortened formal depth from 17 to 9
2023-07-08 10:19:58 +08:00
b3c9bdb650
pass test for timing params with depth of 9
2023-07-06 20:29:50 +08:00
ce3ca7e158
pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters
2023-07-05 16:35:57 +08:00
217770b977
verified precharge and activate cmds, fixed bug in write_calib cmd
2023-07-02 06:38:33 +08:00
760c75d238
passes optimized pipeline stall control and passed fwb_slave properties
2023-06-29 12:56:24 +08:00
2cfbba6d28
change ff to unix
2023-06-24 08:04:21 +08:00
2221a739db
add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave
2023-06-24 07:46:09 +08:00
0ffdacf6e7
add logic for write wb_ack, wb_sel, and aux
2023-06-22 19:49:05 +08:00
0923fdc0b6
add formal assertions using fifo to prove every wb request has a corresponding read/write command output
2023-06-15 17:43:15 +08:00
053a511144
set write-to-read delay for all banks for every write
2023-06-10 08:19:16 +08:00
c3707dab53
made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
2023-06-08 11:01:56 +08:00
6127bba77a
fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk
2023-06-01 19:18:41 +08:00
9e529131c0
fixed error "added_read_pipe has multiple drivers"
2023-05-29 20:52:48 +08:00
a56e6a8a24
changed write calibration pattern with high autocorrel stat
2023-05-29 16:40:41 +08:00
ab26902f7a
include only the controller (phy is now a separate module)
2023-05-28 16:18:14 +08:00
1e89a236df
fixed implementation errors in Vivado
2023-05-25 19:13:30 +08:00
8e6c422689
complete read and write calibration
2023-05-18 10:45:26 +08:00
c33bc40bd3
Update ddr3_controller.v
2023-05-11 15:35:34 +08:00
9be5b5a616
Update ddr3_controller.v
2023-05-11 14:49:47 +08:00
f3c4b1b465
Update ddr3_controller.v
2023-05-10 15:23:48 +08:00
c0172c24a3
added read phy interface
2023-04-27 19:40:35 +08:00
a5b14accf4
added PHY interface
2023-04-20 19:37:15 +08:00
060a0373e9
Update ddr3_controller.v
2023-04-06 19:56:55 +08:00
3b110018c7
Update ddr3_controller.v
2023-04-06 19:43:32 +08:00
fec8b5b3fc
Update ddr3_controller.v
2023-04-06 19:01:02 +08:00
ae201bfd04
removed irrelevant comments
2023-03-30 19:18:55 +08:00
192a9950e4
applied :retab
2023-03-30 18:27:58 +08:00
fa5fcc2615
use a 4-bit counter plus a 4-bit mask for tracking delay in every bank
...
this is the optimized delay-tracking mechanism on which the 32-bit shift regs is replaced by a 4-bit counter plus a 4-bit mask. This uses lower resources but still able to track the delays and the exact slot number where the delay is already satisfied (hence no added latency)
2023-03-30 18:17:46 +08:00
fa3f5e0d65
use 32-bit shift reg for tracking delay inside every bank
...
There are 4 delays being tracked (delay_before_precharge, delay_before_activate, delay_before_read, and delay_before_write) and 8 banks, that means 32x4x8 = 1024 bits needed for this tracking delay mechanism (totally wasteful!)
2023-03-30 18:14:09 +08:00
73e5f6b3de
added begin-end in short if-else statement
2023-03-23 20:35:37 +08:00
97092cf869
added logic for refresh sequence and bank access
2023-03-23 20:17:12 +08:00
adb21070d4
used :retab and fixed tab spacing
2023-03-09 18:14:58 +08:00
c5d387fa24
added reset sequence and formal assertions
...
- completed (mostly) the reset sequence
- added formal assertions and cover statements for reset sequence logic
- moved all parameters to this file
- fixed port widths
- converted IO ports to ANSI
2023-03-09 18:06:53 +08:00
3633613c47
Update ddr3_controller.v
2023-03-02 20:12:28 +08:00
38109d8297
added initial RTLs
2023-03-02 20:04:37 +08:00
AngeloJacobo